Input of test conditions and output generation for built-in self test
A system and method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The present invention employs a flash memory having BIST circuit for testing the memory and a BIST interface circuit adapted to adjust the test conditions of the memory tests. The BIST interface circuit is operable to receive one or more global variables associated with the test conditions of a plurality of tests used on the flash memory and to output results of the memory tests based on the value of the variables. The global variables are used to adjust the test conditions and to trim one or more references used in various flash memory tests and operations. The system may further include a serial communications medium for communicating the global variables to the BIST interface and test results from the interface.
1. A system for providing programmable test conditions for a built-in self test circuit of a memory device, the system comprising:
a flash memory;
a BIST interface circuit adapted to receive one or more global variables associated with the test conditions of a plurality of memory tests used on the flash memory and to output results of the memory tests based on the value of the variables, wherein the global variables are shared between the plurality of memory tests; and
wherein the global variables comprise one or more of:
a drain voltage, a gate voltage, a reference voltage, a reference current, a number of pulses used in a checker board pattern test, a number of pulses used in a diagonal pattern test, a number of pulses used in an erase test, a number of pulses used in a zeroes program test, a repair/no repair selection, a program stress and read/read only selection, and a pattern to be used during a read test; and
wherein test conditions associated with the global variables comprise:
a drain voltage value, a gate voltage value, a reference voltage value, a reference current value, a maximum number of pulses used in a checker board pattern test, a maximum number of pulses used in a diagonal pattern test, a maximum number of pulses used in an erase test, a maximum number of pulses used in a zeroes program test, selection of one of a repair/no repair, selection of one of a program stress and read/read only, and selection of one of a read test pattern, respectively; and
wherein the BIST interface circuit is adapted to adjust one or more test conditions of the shared global variables based on one or more earlier test results and use the adjusted one or more test conditions in an additional test; and
a BIST circuit adapted to test operations of the flash memory based on the value of the variables programmed into the test conditions and to report results of the memory tests.
2. The system of claim 1 , further comprising a communications medium for communicating the global variables to the BIST interface and test results from the interface.
3. The system of claim 2 , wherein the communications is between the BIST interface and automated test equipment located external to an integrated circuit comprising the BIST circuit.
4. The system of claim 2 , wherein the communications medium is a serial communications medium.
5. The system of claim 4 , wherein the serial communications is accomplished between the BIST interface and automated test equipment located external to an integrated circuit comprising the BIST circuit.
6. The system of claim 4 , wherein each global variable used in the serial communications is associated with a default variable value.
7. The system of claim 6 , wherein the value of each global variable further comprises an offset value associated with the default value.
8. The system of claim 7 , wherein the global variable is represented by a multi-bit binary code for computing a programmed number of steps of offset from the default value.
9. The system of claim 6 , wherein the default value of each global variable is hardwired in the circuit.
10. The system of claim 4 , wherein a global variable used in the serial communications medium represents a voltage value.
11. The system of claim 4 , wherein the serial communications comprises a predetermined command sequence comprising:
a first predetermined test code before a global variable sequence; and
a second predetermined test code before an on/off test indications sequence.
12. The system of claim 11 , wherein the first and second predetermined test codes are multi-bit binary code representations.
13. The system of claim 11 , wherein the predetermined on/off test indications are one-bit binary code representations wherein a first state deactivates the test and a second state activates the test.
14. The system of claim 11 , wherein the serial communications further comprises a test results sequence comprising:
a predetermined sequence of test result indications, wherein the testing result of each test is represented by a result code.
15. The system of claim 14 , wherein the test result indications are reported by the BIST circuit and output from the BIST interface, and wherein such test result indications are in an order associated with an input test sequence.
16. The system of claim 11 , wherein the command sequence and the test sequence are divided into two or more corresponding portions.
17. The system of claim 1 , wherein the BIST interface circuit comprises:
a state machine coupled to the BIST circuit for executing test sequences according to test conditions established by the global variables;
an input buffer to communicate the global variables to the state machine; and
an output buffer to communicate the results of the tests executed from the state machine.
18. The system of claim 17 , wherein the communications with the BIST interface is a serial communications medium.
19. The system of claim 17 , wherein the serial communications is accomplished between the BIST interface and automated test equipment located external to an integrated circuit comprising the BIST circuit.
20. The system of claim 1 , wherein the BIST interface is adapted to execute a test sequence on more than one BIST circuit.
21. The system of claim 1 , further comprising at least one redundant circuit provided for repair purposes based on results of the test operations.
22. The system of claim 21 , wherein the BIST interface is adapted to direct the BIST circuit to repair a failure.
23. The system of claim 21 , wherein the BIST circuit is configured to repair or replace a failed memory cell.
24. The system of claim 23 , wherein the interactive adjustment of the test conditions comprises adjusting the test conditions of subsequent tests based on the test results reported by a first test and shared among the plurality of tests using the global variables.
25. The system of claim 1 , wherein the system is adapted to direct the BIST circuit to repair a failure via automated test equipment located external to an integrated circuit comprising the BIST circuit.
26. The system of claim 1 , wherein the one or more global variables comprise one or more bits of a multi-bit code corresponding to the one of a drain voltage, a gate voltage, a reference voltage, a reference current, a number of pulses used in a checker board pattern test, a number of pulses used in a diagonal pattern test, a number of pulses used in an erase test, a number of pulses used in a zeroes program test, a repair/no repair selection, a program stress and read/read only selection, and a pattern to be used during a read test.
27. The system of claim 1 , wherein the value of each global variable comprises a default value offset by a programmed value corresponding to one of a drain voltage value, a gate voltage value, a reference voltage value, a reference current value, a maximum number of pulses used in a checker board pattern test, a maximum number of pulses used in a diagonal pattern test, a maximum number of pulses used in an erase test, a maximum number of pulses used in a zeroes program test, selection of one of a repair/no repair selection, selection of one of a program stress and read/read only selection, and selection of one of a read test pattern, respectively.
28. The system of claim 27 , wherein the global variables are input by a user during operations of a memory test.
29. The system of claim 1 , wherein the BIST interface is an integral portion of the BIST circuitry.
30. The system of claim 1 , wherein the global variables are further used to trim a voltage or current reference used in one or more flash memory tests and operations.
31. The system of claim 1 , wherein the global variables are further operable to interactively adjust the test conditions used in the plurality of flash memory tests and operations thereof, wherein results obtained from a first test are used to adjust test conditions for other tests by way of the shared global variables.
32. The system of claim 31 , wherein the interactive adjustment of the test conditions comprises adjusting the test conditions of a second test based on the test results reported after a first test.
33. A system for providing programmable test conditions for a built-in self test circuit of a memory device, the system comprising:
a flash memory;
a BIST interface circuit adapted to receive one or more global variables associated with the test conditions of a plurality of memory tests used on the flash memory and to output results of the memory tests based on the value of the variables, wherein the global variables are shared between the plurality of memory tests and are used to adjust the test conditions of the flash memory tests and operations thereof;
a BIST circuit adapted to test operations of the flash memory based on the value of the variables programmed into the test conditions and to report results of the memory tests; and
a serial communications medium for communicating the global variables to the BIST interface and test results from the interface, wherein the serial communications comprises a predetermined command sequence comprising:
a first predetermined test code before a global variable sequence;
a second predetermined test code before an on/off test indications sequence; and
a test results sequence comprising a predetermined sequence of test result indications, wherein the testing result of each test is represented by a result code, and wherein the test result indications are two-bit binary code representations comprising:
00=Pass
01=Fail
10=Pass with Repair
11=Fail with Repair.
34. A system for providing programmable test conditions for a built-in self test circuit of a memory device, the system comprising:
a flash memory comprising an array of memory cells;
a BIST interface circuit adapted to receive one or more global variables associated with the test conditions of a plurality of memory tests used on the flash memory and to output results of the memory tests based on the value of the variables, wherein the global variables are shared between the plurality of memory tests and are used to adjust the test conditions of the flash memory tests and operations thereof;
a BIST circuit adapted to test operations of the flash memory based on the value of the variables programmed into the test conditions and to report results of the memory tests; and
a serial communications medium for communicating the global variables to the BIST interface and test results from the interface, wherein the serial communications comprises a predetermined command sequence comprising:
a first predetermined test code before a global variable sequence; and
a second predetermined test code before an on/off test indications sequence, wherein the serial communications further comprises a test results sequence comprising a predetermined sequence of test result indications, and wherein the test result indications are two-bit binary code representations comprising:
00=Pass
01=Fail
10=Pass with Repair
11=Fail with Repair.