MOS transistor and method for producing a MOS transistor structure
View Patent ↗A MOS transistor, and a method for producing the same, is provided with a source region, a gate-region, a drain region, and a drift region in an SOI wafer. The SOI-wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region. Whereby, the active semiconductor layer, at least in a portion of the drift region, is thicker than in the source region. The MOS transistor is characterized in that the active semiconductor layer, in a vertical direction, is completely separated by the insulating intermediate layer from the carrier layer.
1. A MOS transistor comprising:
a source region;
a gate region;
a drain region; and
a drift region in an SOI wafer,
wherein the SOI wafer has a carrier layer, which carries an insulating intermediate layer,
wherein the insulating intermediate layer carries an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region,
wherein the active semiconductor layer, at least in a portion of the drift region, is thicker than in the source region, and further wherein the active semiconductor layer in the portion of the drift region, in which the active semiconductor layer is thicker than in the source region, extends more deeply into the carrier layer than in the source region; and
wherein the active semiconductor layer in a vertical direction is completely separated from the carrier layer by the insulating intermediate layer.
2. The MOS transistor according to claim 1 , wherein the active semiconductor layer has a planar structure on a surface thereof.
3. The MOS transistor according to claim 1 , wherein a transition from a first thickness of the active layer in the source region to a second thickness in a portion of the drift region, in which the active semiconductor layer is thicker than in the source region, occurs in steps.
4. The MOS transistor according to claim 1 , wherein a transition from a first thickness of the active layer in the source region to a second thickness in the portion of the drift region, in which the active semiconductor layer is thicker than in the source region ( 20 ), occurs continuously.
5. The MOS transistor according to claim 4 , wherein the continuous transition occurs parallel to a crystal plane of the active semiconductor layer.
6. The MOS transistor according to claim 1 , wherein the active semiconductor material in the portion of the drift region, in which the active semiconductor layer is thicker than in the source region, has a lateral doping material concentration gradient.
7. The MOS transistor according to claim 1 , wherein a single-crystal silicon is a starting material for the active semiconductor layer.
8. A transistor comprising:
a carrier layer;
an active semiconductor layer having a source region, a gate region, a drain region, and a drift region; and
an insulating intermediate layer being provided between the carrier layer and the active semiconductor layer,
wherein the active semiconductor layer is thicker in an area that is at least partially defined by the drift region than in an area that is at least partially defined by the source region, the thickness of the active semiconductor layer being substantially perpendicular to a plane formed by the active semiconductor layer, and further wherein the active semiconductor layer in the portion of the drift region, in which the active semiconductor layer is thicker than in the source region, extends more deeply into the carrier layer than in the source region; and
wherein the insulating intermediate layer completely insulates the active semiconductor layer from the carrier layer.