Structure and method of integrating compound and elemental semiconductors for high-performance CMOS
View Patent ↗A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.
1. A method of fabricating a semiconductor substrate comprising the steps of:
forming a compound semiconductor substrate having a bulk material, a first layer on top of the bulk material and a second layer on top of the first layer formed of the bulk material;
forming a third layer of a non-crystalline material on top of the second layer;
removing a portion of the third layer and the second layer down to the first layer;
epitaxially growing an elemental semiconductor layer on the first layer adjacent to a remaining portion of the second layer, such that a height of the elemental semiconductor layer is substantially the same as the remaining portion of the second layer;
removing the third layer;
forming an insulating layer over the second layer and the elemental semiconductor layer to form a first substrate; and
wafer bonding the first substrate onto a monocrystalline substrate, such that the insulating layer bonds to the monocrystalline substrate.
2. The method as recited in claim 1 , further comprising the step of removing the bulk material and the first layer of the compound semiconductor substrate.
3. The method as recited in claim 1 , wherein after the step of forming an insulating layer over the second layer and the elemental semiconductor layer to form a first substrate the step of planarizing the insulating layer is performed.
4. The method as recited in claim 1 , wherein the insulating layer includes portions formed on the first substrate and on the monocrystalline substrate and the step of wafer bonding includes bonding the portions of the insulating layer.
5. The method as recited in claim 1 , wherein said elemental semiconductor is substantially lattice-matched to the compound semiconductor substrate.
6. The method as recited in claim 1 , wherein the elemental semiconductor includes at least one of SiGe, SiGeC, or Ge, the compound semiconductor substrate includes GaAs, the first layer includes AIGaAs, and the second layer includes GaAs or InGaAs.