IP Library Granted Patent US 7,579,631
Granted Patent B2
US 7,579,631 · App. 11/087,000 · Granted Aug 25, 2009

Variable breakdown characteristic diode

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Quick Facts
Patent No.
US 7,579,631
App. No.
11/087,000
Granted
Aug 25, 2009
Kind
B2
Abstract

A memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes is disclosed. The controllably conductive media includes a passive layer made of super ionic material and an active layer. When an external stimuli, such as an applied electric field, is imposed upon the first and second electrode, ions move and dope and/or de-dope the polymer. The applied external stimuli used to dope the polymer is larger than an applied external stimuli to operate the memory cell. The polymer functions as a variable breakdown characteristic diode with electrical characteristics which are a consequence of the doping degree. The memory element may have a current limited read signal. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers, hand-held electronic devices and memory devices containing the memory cell(s) are also disclosed.

Claims (38)

1. A method of controlling a memory cell comprising:

providing a controllably conductive media between a first electrode and at least a second electrode, the controllably conductive media comprising at least one active layer having a breakdown voltage and at least one passive layer comprising super ionic material;

doping the active layer; and

altering a state of the memory cell by changing the breakdown voltage of the at least one active layer from a first value to a second value, each value is associated with a different state of the memory cell.

2. The method of claim 1 , wherein doping the active layer further comprises:

applying an external stimuli having a first polarity;

causing dopant to move from the passive layer to the active layer;

reducing the breakdown voltage of the active layer;

placing the memory cell in a program state.

3. The method of claim 2 , further comprising:

applying an external stimuli having a second polarity and a magnitude slightly larger than the reduced breakdown voltage; and

placing the memory cell in a read state.

4. The method of claim 2 , further comprising:

applying an external stimuli having a second polarity;

de-doping the active layer; and

placing the memory cell in an erase state.

5. The method of claim 4 , wherein de-doping the active layer comprises causing the dopant to move from the active layer to the passive layer.

6. The method of claim 1 , the breakdown voltage is determined by the doping level of the active layer.

7. The method of claim 6 , the doping level determines the electrical characteristics of the memory cell.

8. The method of claim 1 , wherein the super ionic material is selected from the group consisting of Cu 2 S, CuS, Ag 2 S, CuO, Cu 2 O, Cu 2 Se, Ag 2 Se and TiSe 2 .

9. The method of claim 1 , the active layer has operating characteristics of a Zener diode.

10. The method of claim 1 , wherein the active layer comprises one of an organic semiconductor material, an inorganic semiconductor material and a mixture of organic and inorganic semiconductor material.

11. The method of claim 1 , wherein the passive layer comprises at least one conductivity facilitating compound.

12. A method of controlling a memory cell, comprising:

providing a first electrode and at least a second electrode;

placing a controllably conductive media between the first electrode and the at least a second electrode, the controllably conductive media comprises a super ionic layer and an active layer having a first breakdown voltage level and at least a second breakdown voltage level, and

selectively modifying a value of an applied external stimuli between the first breakdown voltage level and at least the second breakdown voltage level to change the electrical characteristics of the memory cell, wherein each breakdown voltage level corresponds to a different state of the memory cell.

13. The method of claim 12 , modifying the value of the external stimuli from the first breakdown voltage level to the at least a second breakdown voltage level erases the memory cell.

14. The method of claim 12 , modifying the value of the external stimuli from the at least a second breakdown voltage level to a value slightly above the first breakdown voltage level programs the memory cell.

15. The method of claim 12 , further comprising selecting a material of the active layer from at least one of an organic semiconductor material, an inorganic semiconductor material or a mixture of organic and inorganic semiconductor material.

16. The method of claim 12 , further comprising selecting a material of the superior ionic material from the group consisting of Cu 2 S, CuS, Ag 2 S, CuO, Cu 2 O, Cu 2 Se, Ag 2 Se and TiSe 2 .

17. The method of claim 12 , selectively modifying the value of the external stimuli from the first breakdown voltage level to the at least a second breakdown voltage level causes a traveling erase voltage to provide a relatively fast erase of the memory cell.

18. The method of claim 12 , further comprising selectively changing the controllably conductive media to at least one of conductive, semiconductive, or nonconductive in a controllable manner with the applied external stimuli.

19. The method of claim 12 , applying the external stimuli in a first direction causes doping of the active layer, placing the memory cell in a programming state.

20. The method of claim 19 , applying the external stimuli in a second direction causes de-doping of the active layer, placing the memory cell in an erase state.

21. A computer that employs the method of claim 12 .

22. A hand-held electronic device that employs the method of claim 12 .

23. A memory device comprising an array of the memory cells that employ the method of claim 12 .

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036044/0122 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2005
From: GAUN, DAVID; BILL, COLIN S.; KAZA, SWAROOP
To: SPANSION LLC
Reel/Frame 016944/0252 →