Compound semiconductor device and manufacturing method thereof
View Patent ↗A pad electrode of a field effect transistor is formed solely of a pad metal layer without providing a gate metal layer. A high concentration impurity region is provided below the pad electrode, and the pad electrode is directly contacted to a substrate. Predetermined isolation is ensured by the high concentration impurity region. Accordingly, in a structure not requiring a nitride film as similar to the related art, it is possible to avoid defects upon wire boding attributing to hardening of the gate metal layer. Therefore, in the case of a buried gate electrode structure for enhancing characteristics of the field effect transistor, it is possible to enhance reliability and yields.
1. A compound semiconductor device comprising:
a compound semiconductor substrate;
a channel layer formed in the substrate;
a source region and a drain region that are formed in the substrate and adjacent the channel layer;
a gate electrode made of a gate metal layer and in contact with the channel layer;
a source electrode comprising a first source electrode made of an ohmic metal layer and in contact with the source region and a second source electrode made of a pad metal layer and disposed on the first source electrode;
a drain electrode comprising a first drain electrode made of the ohmic metal layer and in contact with the drain region and a second drain electrode made of the pad metal layer and disposed on the first drain electrode;
a pad electrode made of the pad metal layer and in direct physical contact with the substrate, the pad metal layer comprising a metal not included in the gate metal layer; and
a high concentration impurity region formed in the substrate and adjacent the pad electrode.
2. The compound semiconductor device of claim 1 , wherein the gate electrode is partially buried in the substrate.
3. The compound semiconductor device of claim 1 , wherein the pad electrode is in contact with the high concentration impurity region, and part of the high concentration impurity region is not covered by the pad electrode.
4. The compound semiconductor device of claim 1 , wherein the pad electrode is separated from the high concentration impurity region so that a separation between the pad electrode and the high concentration impurity region is such that a current flow is maintained under an application of direct current.
5. The compound semiconductor device of claim 1 , further comprising an insulating film that is disposed on the source region for an alignment of the source region or disposed on the drain region for an alignment of the drain region.
6. The compound semiconductor device of claim 1 , wherein the high concentration impurity region is configured to suppress an expansion of a depletion layer extending from the pad electrode.
7. The compound semiconductor device of claim 1 , wherein the pad electrode is configured to transmit an analog signal in a gigahertz range.
8. The compound semiconductor device of claim 1 , wherein an impurity concentration of the high concentration impurity region is 1×10 17 cm −3 or higher.
9. The compound semiconductor device of claim 1 , wherein the pad electrode is disposed on the high concentration impurity region so that the pad electrode is confined within a lateral boundary of the high concentration impurity region.