Integrated circuit die for wire bonding and flip-chip mounting
View Patent ↗An integrated circuit die carries conductive pads and thereon, the larger pads being suitable for flip-chip assembly and the smaller pads being suitable for wire bond assembly. The pitch between pads is at least the minimum required for flip-chip assembly, whereas the pitch between each of pads and the adjacent pad or pads is at least the minimum required for wire bond assembly. For wire bond assembly a passivation layer exposing all pads is provided, whereas for flip-chip assembly a passivation layer exposes only certain pads so that conductive bumps may be provided. The provision of pads complying with the minimum spacing requirements for both flip-chip and wire bond assembly enables a “dual purpose” (e.g. one set of pads being for normal production and another set for testing purposes) die to be produced without any increase in die size.
1. An integrated circuit die, comprising:
conductive pads disposed on an integrated circuit die, wherein said conductive pads include:
flip-chip pads having a first predetermined center-to-center spacing between each of said flip-chip padsand a nearest adjacent flip-chip pad and
about uniformly sized wire bond pads having a second predetermined center-to-center spacing, less than said first predetermined center-to-center spacing and less than a minimum spacing for said flip-chip pads, between each of said wire bond pads and either a nearest adjacent flip-chip or wire bond, said wire bond pads interspersed between said flip-chip pads; and
a passivation layer exposing said flip-chip pads or exposing both said flip-chip and wire bond pads.
2. The integrated circuit die as recited in claim 1 wherein said flip-chip pads are larger in area than said wire bond pads.
3. The integrated circuit die as recited in claim 1 wherein said conductive pads are disposed in a line adjacent one or more edges of said integrated circuit die.
4. The integrated circuit die as recited in claim 1 wherein said flip-chip pads are disposed in two lines adjacent one or more edges of said integrated circuit die, wherein said flip-chip pads in one of said two lines are disposed in a staggered relationship with respect to said flip-chip pads in the other of said two lines.
5. The integrated circuit die as recited in claim 4 wherein said wire bond pads are disposed in one of said two lines.
6. The integrated circuit die as recited in claim 1 wherein said flip-chip pads are connected to one set of connection points in an integrated circuit, and said wire bond pads are connected to another set of connection points in said integrated circuit.
7. An integrated circuit die, comprising:
conductive pads disposed on an integrated circuit die, wherein said conductive pads include:
about uniformly sized flip-chip pads having a first minimum distance between each of said flip-chip pads and a nearest adjacent flip-chip pad; and
about uniformly sized wire bond pads, wherein each wire bond pad has a second minimum distance between it and its nearest adjacent pads less than a minimum spacing for said flip-chip pads, whether the nearest adjacent pads are flip-chip or wire bond pads, and wherein each flip-chip pad is larger than each wire bond pad; and
a passivation layer exposing said flip-chip pads and said wire bond.