Embedded barrier for dielectric encapsulation
View Patent ↗A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.
1. An electronic device, comprising:
a first diffusion barrier layer;
a first dielectric layer on said fist diffusion barrier layer;
a hardmask layer on portions of said first dielectric layer;
a liner layer on portions of said first dielectric layer, wherein said liner layer is not in contact with said first diffusion barrier layer;
a metal layer on said liner layer, said metal layer protruding above the plane formed by said first dielectric layer and said hardmask layer;
a second diffusion barrier layer contiguous with said hardmask layer and said metal layer, and
a second dielectric layer on said second diffusion barrier layer.
2. The electronic device of claim 1 wherein said second diffusion barrier layer is an SiCNH layer.
3. The electronic device of claim 1 wherein said hardmask layer is SiCOH.
4. The electronic device of claim 1 wherein said first and second dielectric layers are ULK dielectrics.
5. The electronic device of claim 1 wherein said metal layer is a copper layer.