IP Library Granted Patent US 7,291,872
Granted Patent B2
US 7,291,872 · App. 11/193,417 · Granted Nov 6, 2007

Semiconductor device and method for fabricating the same

Assignee: Matsushita Electric Industrial Co., Ltd.
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Quick Facts
Patent No.
US 7,291,872
App. No.
11/193,417
Granted
Nov 6, 2007
Kind
B2
Abstract

In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.

Claims (33)

1. A semiconductor device comprising:

a conductive layer;

a channel layer made of III-V nitride semiconductor and formed on or over the conductive layer;

a Schottky layer made of III-V nitride semiconductor and formed on the channel layer;

a first source electrode, a drain electrode, and a gate electrode formed on different parts of the Schottky layer, respectively;

a second source electrode connected to the first source electrode; and

an interconnect member connecting the first source electrode to the conductive layer through a groove penetrating the channel layer and the Schottky layer.

2. The device of claim 1 ,

wherein the conductive layer is a conductive substrate, and

the device further comprises a buffer layer interposed between the conductive substrate and the channel layer.

3. The device of claim 1 , further comprising:

an insulator substrate or a semiconductor substrate provided below the conductive layer; and

a buffer layer interposed between the substrate and the conductive layer or between the conductive layer and the channel layer.

4. The device of claim 1 ,

wherein the gate electrode is provided in a region interposed between the first source electrode and the drain electrode, and

the second source electrode extends from a region above the first source electrode toward a region above the drain electrode.

5. The device of claim 4 ,

wherein a portion of the second source electrode extending from the region above an edge of the gate electrode closer to the drain toward the region above the drain electrode has a length of 20% or more of the distance between the gate electrode and the drain electrode.

6. The device of claim 1 ,

wherein the gate electrode has a T-shaped cross section including: a stem in contact with the Schottky layer; and a top wider than the stem.

7. The device of claim 1 ,

wherein a metal in ohmic contact with the conductive layer is formed between the bottom surface of the groove and the interconnect member.

8. The device of claim 7 ,

wherein the metal is formed in a single layer, a stack of layers, or an alloy containing at least one of aluminum, titanium, gold, germanium, and antimony.

9. The device of claim 7 ,

wherein the Schottky layer is made of a material different from the conductive layer,

the metal is made of a material different from the first source electrode, and

the first source electrode is in ohmic contact with the Schottky layer.

10. The device of claim 9 , wherein the metal is made of the same material as the interconnect member.

11. The device of claim 9 , wherein the first source electrode is made of a material different from the interconnect member.

12. The device of claim 11 , wherein the second source electrode is made of a material different from the interconnect member.

13. The device of claim 4 , wherein the first source electrode is made of a material different from the second source electrode.

14. The device of claim 9 , wherein the first source electrode is not formed directly above the groove.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: INFINEON TECHNOLOGIES AUSTRIA AG
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 072853/0508 →
CHANGE OF NAME Recorded Dec 13, 2024
From: PANASONIC CORPORATION
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 069631/0392 →
CHANGE OF NAME Recorded Dec 6, 2024
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 069530/0869 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2005
From: HIKITA, MASAHIRO; UENO, HIROAKI; HIROSE, YUTAKA; YANAGIHARA, MANABU; UEMOTO, YASUHIRO; TANAKA, TSUYOSHI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 016830/0185 →
Priority Claims (1)
JP 2004-270925 · Sep 17, 2004 · national
Continuity (1)
Related Publication 20060060895A1 · Mar 23, 2006