Methods for fabricating semiconductor devices and contacts to semiconductor devices
View Patent ↗Methods for fabricating semiconductor structures and contacts to semiconductor structures are provided. A method comprises providing a substrate and forming a gate stack on the substrate. The gate stack is formed having a first axis. An impurity doped region is formed within the substrate adjacent to the gate stack and a dielectric layer is deposited overlying the impurity doped region. A via is etched through the dielectric layer to the impurity doped region. The via has a major axis and a minor axis that is perpendicular to and shorter than the major axis. The via is etched such that the major axis is disposed at an angle greater than zero and no greater than 90 degrees from the first axis. A conductive contact is formed within the via.
1. A semiconductor structure comprising:
a substrate;
two parallel gate stacks on said substrate, wherein said two parallel gate stacks are oriented parallel to a first axis;
an impurity doped region disposed between said two parallel gate stacks;
a dielectric layer disposed overlying said impurity doped region, said dielectric layer having a via extending therethrough to said impurity doped region;
a conductive contact that is disposed entirely within said via of said dielectric layer and is electrically coupled to said impurity doped region, wherein said conductive contact has a major axis and a minor axis that is perpendicular to and shorter than said major axis, and wherein said major axis is disposed at an angle greater than zero and less than 90 degrees from said first axis.
2. The semiconductor structure of claim 1 , wherein each of said two parallel gate stacks comprises a portion of a flash EEPROM memory array.
3. The semiconductor structure of claim 1 , wherein said major axis is disposed at angle in the range of about 30 degrees to about 60 degrees from said first axis.
4. The semiconductor structure of claim 3 , wherein said angle is approximately 45 degrees from said first axis.
5. The semiconductor structure of claim 1 , wherein said conductive contact has an elliptical shape.
6. The semiconductor structure of claim 1 , wherein each of said two parallel gate stacks comprises:
a tunnel oxide layer;
a floating gate overlying said tunnel oxide;
an interlevel dielectric layer overlying said floating gate; and
a control gate overlying said interlevel dielectric layer.
7. The semiconductor structure of claim 1 , further comprising two parallel STI lines disposed within said substrate and substantially perpendicular to and underlying said two parallel gate stacks.
8. The semiconductor structure of claim 7 , wherein said impurity doped region comprises a drain region that is bounded by said two parallel STI lines and said two parallel gate stacks.