IP Library Patent Application 11295676
Patent Application
App. No. 11/295,676

Network topology for a scalable multiprocessor system

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Quick Facts
Patent No.
US None
App. No.
11/295,676
Filed
Dec 6, 2005
Art Unit
2181
USPC
712/11
Abstract

A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

Claims (14)

1 . A massively parallel processing system comprising:

a plurality of processing element nodes;

a scalable interconnection network comprising:

a plurality of physical communication links; and

a plurality of first level routers for interconnecting the plurality of processing element nodes in a cluster; and

one or more metarouters for interconnecting the plurality of first level routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

2 . The massively parallel processing system of claim 1 wherein each one of the clusters is a two-dimensional hypercube.

3 . The massively parallel processing system of claim 1 wherein each one of the metarouters are eight port routers.

4 . The massively parallel processing system of claim 1 wherein each one of the metarouters are four port routers.

5 . The massively parallel processing system of claim 1 wherein each one of the processing element nodes comprises four processors.

6 . A massively parallel processing system comprising:

a plurality of processors;

a first set of routers for interconnecting the plurality of processors as two-dimensional hypercubes; and

a second set of routers for interconnecting the first set of routers wherein the hypercubes remain in tack as the system is expanded.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2017
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 044128/0149 →
MERGER Recorded Oct 24, 2016
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040105/0988 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2016
From: SILICON GRAPHICS, INC.
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 040264/0138 →
CHANGE OF NAME Recorded Oct 24, 2016
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 040264/0202 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2016
From: DENEROFF, MARTIN M; THORSON, GEORGE M; PASSINT, RANDAL S
To: SILICON GRAPHICS, INC.
Reel/Frame 040106/0040 →
CHANGE OF NAME Recorded Oct 21, 2016
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 040459/0157 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2016
From: SILICON GRAPHICS, INC
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 040459/0026 →
MERGER Recorded Oct 21, 2016
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040459/0518 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2007
From: GENERAL ELECTRIC CAPITAL CORPORATION
To: MORGAN STANLEY & CO., INCORPORATED
Reel/Frame 019995/0895 →
SECURITY INTEREST Recorded Oct 24, 2006
From: SILICON GRAPHICS, INC.
To: GENERAL ELECTRIC CAPITAL CORPORATION
Reel/Frame 018545/0777 →