MRAM memory with residual write field reset

1. A method of writing a memory cell of an MRAM, comprising:

applying a first magnetic field to a memory cell during a first time period, the first magnetic field having a first direction and a first magnitude;

applying a second magnetic field to the memory cell during a second time period, the second magnetic field having a second direction and a second magnitude, wherein a start of the second time period follows a start of the first time period; wherein an end of the second time period follows an end of the first time period, and wherein the first time period overlaps the second time period; and

applying a third magnetic field to the memory cell during a third time period, wherein the third time period overlaps at least a portion of the second time period, the third magnetic field having a third direction and a third magnitude,

wherein a start of the third time period follows the end of the first time period, and

wherein the third direction of the third magnetic field is approximately opposite to the first direction of the first magnetic field.

2. A method as in claim 1 , wherein the second magnitude of the second magnetic field is greater than the third magnitude of the third magnetic field.

3. A method as in claim 1 , wherein the first magnitude of the first magnetic field is greater than the third magnitude of the third magnetic field.

4. A method as in claim 1 , wherein an end of the third time period is at or before the end of the second time period.

5. A method as in claim 1 , wherein an end of the third time period is after the end of the second time period.

6. A method as in claim 1 , wherein applying the first magnetic field and applying the third magnetic field further comprise passing current through a same first conductor in the memory cell, and applying the second magnetic field further comprises passing current through a second conductor in the memory cell, wherein the second conductor is different than the first conductor.

7. A method as in claim 1 , wherein the third magnitude of the third magnetic field is approximately equal to or greater than a magnitude of a residual magnetic field.

8. A method as in claim 1 , wherein,

the applying the first magnetic field comprises passing a first current through a first conductor in the memory cell in a first direction at a first current level,

the applying the second magnetic field comprises passing a second current through a second conductor in the memory cell in a second direction at a second current level, and

the applying the third magnetic field comprises passing a third current through the first conductor in the memory cell in a third direction at a third current level,

wherein the third direction is opposite the first direction.

9. An MRAM, comprising:

an MRAM array comprising a plurality of MRAM cells; and

write circuitry for writing a memory cell of the plurality of MRAM cells,

wherein the write circuitry comprises:

a first driver coupled to the memory cell for passing a first current through a first current path of the memory cell;

a second driver coupled to the memory cell that passes a second current through a second current path of the memory cell;

a third driver coupled to the memory cell for passing a third current through the first current path,

wherein the third current flows in an opposite direction relative to the first current; and

control circuitry that enables the first driver during a first time period, and that enables both the first driver and the second driver during a second time period and the third driver during a third time period, wherein at least a portion of the third time period overlaps with the second time period.

10. An MRAM as in claim 9 , wherein a start of the first time period is before a start of the second time period, an end of the first time period is before an end of the second time period, the second time period overlaps the first time period, and a start of the third time period is after the end of the first time period.

11. An MRAM as in claim 9 , further comprising:

a first bias circuit, coupled to the first driver, the first bias circuit controlling a magnitude of the first current; and

a second bias circuit, coupled to the third driver, the second bias circuit controlling a magnitude of the third current.

12. An MRAM as in claim 9 , wherein the first driver comprises a first transistor of a first conductivity type for providing the first current, and wherein the third driver comprises a second transistor of a second conductivity type for providing the third current.

13. An MRAM as in claim 12 , wherein the first conductivity type of the first transistor comprises n-channel and the second conductivity type of the second transistor comprises p-channel.

14. An MRAM, comprising:

an MRAM array comprising a plurality of MRAM cells; and

write circuitry for writing a memory cell of the plurality of MRAM cells,

wherein the write circuitry comprises:

a first driver coupled to the memory cell for passing a first current through a first current path of the memory cell;

a second driver coupled to the memory cell that passes a second current through a second current path of the memory cell;

wherein the first driver also passes a third current through the first current path in an opposite direction relative to the first current; and

control circuitry that enables the first driver during a first time period, that enables the second driver during a second time period and the first driver during a third time period, wherein at least a portion of the third time period overlaps with the second time period.

15. An MRAM as in claim 14 , wherein a start of the first time period is before a start of the second time period, an end of the first time period is before an end of the second time period, the second time period overlaps the first time period, and a start of the third time period is after the end of the first time period.

16. An MRAM as in claim 14 , further comprising:

a first bias circuit, coupled to the first driver, the first bias circuit controlling a magnitude of the first current; and

a second bias circuit, coupled to the first driver, the second bias circuit controlling a magnitude of the third current.

17. A storage circuit, comprising:

a first current conductor;

a second current conductor oriented orthogonal to the first current conductor;

a magnetic tunnel junction situated between the first current conductor and the second current conductor; wherein a first current having a first direction is provided in the first current conductor during a first time period, and wherein a second current having a second direction is provided in the second current conductor during a second time period, and

wherein a third current having a third direction which is opposite the first direction is provided in the first current conductor during at least a portion of the second time period.

18. A storage circuit as in claim 17 , wherein a magnitude of the second current is greater than a magnitude of the third current, and wherein the magnitude of the first current is greater than a magnitude of the third current.

19. A storage circuit as in claim 17 , wherein a start of the first time period is before a start of the second time period, an end of the first time period is before an end of the second time period, and the second time period overlaps the first time period.

20. An MRAM, comprising:

an MRAM array comprising a plurality of MRAM cells; and

write circuitry for writing a memory cell of the plurality of MRAM cells,

wherein the write circuitry comprises:

a first driver coupled to the memory cell for passing a first current through a first current path of the memory cell;

a second driver coupled to the memory cell that passes a second current through a second current path of the memory cell;

a third driver coupled to the memory cell for passing a third current through the second current path,

wherein the third current flows in an opposite direction relative to the second current; and

control circuitry that enables the first driver during a first time period, and that enables at least one of the first driver and the second driver during a second time period and the third driver during a third time period.