Method and apparatus for generating memory models and timing database
A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
1. A memory timing database recorded on a computer-readable medium and accessible by a computer, the database comprising:
timing characteristics for each of a plurality of different tiling netlists described by triple (MEM, Memory Resource, tiling_variant), wherein Memory Resource identifies a memory resource on an integrated circuit, MEM identifies a characterization memory of a set of characterization memories having different variants of tiling a specific design memory to the Memory Resource, and tiling_variant identifies the variant of tiling MEM to Memory Resource, wherein the timing characteristics comprise, for each tiling netlist:
evaluated timing characteristics corresponding to a first subset of combinations of input ramptimes and output loads of the tiling netlist; and
estimated timing characteristics corresponding to a second, different subset of combinations of input ramptimes and output loads of the tiling netlist, which are mathematical functions of at least one or more of the timing characteristics for the first subset.
2. The memory timing database of claim 1 wherein the timing characteristics of the first and second subsets comprise, for each tiling netlist:
setup and hold times for inputs to the characterization memory for the input ramptimes; and
input-output path delays through the characterization memory for the combinations of input ramptimes and output loads for the characterization memory.
3. The memory timing database of claim 1 wherein each Memory Resource comprises a reconfigurable random access memory (RRAM).
4. The memory timing database of claim 1 and further comprising:
a worst-case timing database for each characterization memory of each of a plurality of Memory Resources on the integrated circuit comprising the worst timing characteristics of the tiling variants of that characterization memory.
5. The memory timing database of claim 1 wherein at least some of the timing characteristics coffesponding to the second subset of input ramptimes and output loads are linear approximations based on at least one or more of the timing characteristics for the first subset.
6. The memory timing database of claim 1 , wherein the timing characteristics comprise:
for each non boundary cell in the tiling netlist:
the evaluated timing characteristics coffesponding to the first subset of combinations of input ramptimes and output loads; and
the estimated timing characteristics coffesponding to the second subset of combinations of input ramptimes and output loads; and
for each boundary cell in the tiling netlist:
evaluated timing characteristics coffesponding to all combinations of the input ramptimes and output loads in the first and second subsets.
7. The memory timing database of claim 1 , wherein:
the first and second subsets belong to a set comprising a set {R 1 <R 2 < . . . <Rn} of input ramptimes and a set {L 1 <L 2 <. . . <Lm} of output loads, where n and m are positive integer variables greater than one;
for non-boundary cells in the tiling netlist, the first subset comprises only pairs (R 1 , L m/2 ), (R n/2 , L /2 ), and (R n , L m/2 ) of input ramptimes and output loads; and
for the non-boundary cells, the second subset comprises other pairs (R i , L j ) of input ramptimes and output loads, for i=1 to n and for j=1 to m.
8. A memory timing database recorded on a computer-readable medium and accessible by a computer, the database comprising:
timing characteristics for each variation of tiling each of a plurality of different characterization memories of a set of different characterization memories that characterize tiling a specific design memory to a memory resource on an integrated circuit, each characterization memory in the set having a different combination of capacity and width, wherein the timing characteristics comprise, for each variation of tiling of each characterization memory:
evaluated timing characteristics input from a timing analysis tool and coffesponding to a first subset of combinations of input ramptimes and output loads of the characterization memory; and
estimated timing characteristics coffesponding to a second, different subset of combinations of input ramptimes and output loads of the characterization memory, which are mathematical functions of at least one or more of the timing characteristics for the first subset.
9. A memory timing database recorded on a computer-readable medium and accessible by a computer, the database comprising:
timing characteristics for each of a plurality of variations of tiling each of a plurality of different characterization memories of a set of different characterization memones that characterize tiling a specific design memory to a memory resource on an integrated circuit, each characterization memory in the set having a different combination of capacity and width, wherein the timing characteristics comprise,
for each variation of tiling of each characterization memory: for each non boundary cell in the tiling netlist:
evaluated timing characteristics input from a timing analysis tool and coffesponding to a first subset of combinations of input ramptimes and output loads of the characterization memory; and
estimated timing characteristics coffesponding to a second, different subset of combinations of input ramptimes and output loads of the characterization memory, which are mathematical functions of at least one or more of the timing characteristics for the first subset;
for each boundary cell in the tiling netlist:
evaluated timing characteristics coffesponding to all combinations of the input ramptimes and output loads in the first and second subsets.