Isolated power domain core regions in platform ASICs
View Patent ↗A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.
1. A platform application specific integrated circuit (ASIC) having a base layer comprising:
a predefined input/output (I/O) region comprising a plurality of first pre-diffused regions disposed in said base layer;
a predefined core region comprising (i) a plurality of second pre-diffused regions disposed in said base layer and (ii) one or more metal layers defining a plurality of power regions, wherein said plurality of power regions are electrically isolated from each other and said one or more metal layers on said base layer are deposited such that each of said plurality of power regions is connected to a respective one of a plurality of supply voltages; and
an R-cell transistor fabric, said R-cell transistor fabric comprising a plurality of R-cells, each R-cell including multiple diffusions, a gate layer and a metal layer forming a five-transistor cell, said five-transistor cell including two n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs), two p-channel metal oxide semiconductor (PMOS) FETs, one small PMOS device, and contact points, wherein said contact points are attached to power, ground, inputs and outputs via upper metal layers.
2. A platform application specific integrated circuit (ASIC) having a base layer comprising:
a predefined input/output (I/O) region comprising a plurality of first pre-diffused regions disposed in said base layer;
a predefined core region comprising a plurality of second pre-diffused regions disposed in said base layer and one or more metal layers defining a plurality of power regions, wherein said plurality of power regions are electrically isolated from each other and said one or more metal layers on said base layer are deposited such that each of said plurality of power regions is connected to a respective one of a plurality of supply voltages; and
a plurality of customizable cells, each customizable cell including multiple diffusions, a gate layer and a metal layer forming a five-transistor cell, said five-transistor cell including two n-channel transistors, two p-channel transistors, one small p-channel device, and contact points, wherein said contact points are attached to power, ground, inputs and outputs via upper metal layers.
3. The platform ASIC according to claim 2 , wherein said one or more metal layers customize said pre-diffused regions of said platform ASIC as a function block in an isolated power domain.
4. The platform ASIC according to claim 3 , wherein said one or more metal layers customize said pre-diffused regions of said platform ASIC as a function block selected from the group consisting of (i) a low jitter phase locked loop (PLL) and (ii) a low jitter delay lock loop (DLL).
5. The platform ASIC according to claim 2 , wherein at least one of said plurality of power regions is powered only part time when said platform ASIC is operating with battery power.
6. The platform ASIC according to claim 2 , wherein at least one of said plurality of power regions is powered down when said platform ASIC is operating with battery power.
7. The platform ASIC according to claim 2 , wherein at least one of said plurality of power regions is configured to operate only when power is available from a source other than a battery.
8. The platform ASIC according to claim 2 , wherein said plurality of power regions in said core region are associated with power and ground I/Os implemented in said I/O region.
9. The platform ASIC according to claim 2 , wherein said platform ASIC comprises a plurality of power grid tiles connected to form said plurality of power regions.
10. The platform ASIC according to claim 2 , wherein one or more of said plurality of power regions are configured for power supply over-driving of circuitry.
11. The platform ASIC according to claim 10 , wherein one or both of voltage headroom and performance of said one or more of said plurality of power regions are responsive to said power supply over-driving.
12. The platform ASIC according to claim 10 , wherein a power consumption of circuitry in one or more of said plurality of power regions is responsive to power supply under-driving of said circuitry.
13. The platform ASIC according to claim 10 , wherein one or more of said plurality of power regions are configured for back-biasing a silicon substrate of said platform ASIC.
14. The platform ASIC according to claim 13 , wherein one or more of (i) a threshold voltage of a device, (ii) a static power consumption of a region and (iii) a performance characteristic of one or more transistors is determined in response to said back-biasing of said silicon substrate of said platform ASIC.
15. The platform ASIC according to claim 2 , wherein at least two of said plurality of power regions are configured to operate at different voltages.
16. The platform ASIC according to claim 2 , wherein:
at least one of said plurality of power regions is configured to operate with battery power;
at least one of said plurality of power regions is powered down when operating with battery power; and
at least one of said plurality of power regions is configured to operate only when power is available from a source other than battery power.