Non-volatile SONOS-type memory device
A semiconductor memory device, firstly, has both the thickness of a tunnel film and that of a top film provided thereon and configured to be in the FN tunneling region (4 nm or more). The data retention characteristics can be improved by configuring both the thickness of a tunnel film and that of a top film to have a thickness of in the FN tunneling region. Secondly, a high-concentration impurity region of a conductivity type the same as that of the substrate is provided in a substrate region arranged between assist gates provided adjacently to each other. The aforementioned high-concentration impurity region makes a depletion layer extremely thin when bias is applied to the assist gates. Hot holes generated between bands in the depletion region are injected into a charge storage region and the holes and electrons make pairs and disappear, enabling easy data erasing.
1. A semiconductor device comprising:
a semiconductor substrate;
a charge storage region including a tunnel oxide film and a storage film provided below a word line and provided above the semiconductor substrate;
assist gates provided on a gate insulating film on the semiconductor substrate;
substantially U-shaped recesses in the semiconductor substrate and located between adjacent assist gates;
source regions provided in the semiconductor substrate below a first portion of each of the assist gates and adjacent to a first one of the substantially U-shaped recesses; and
drain regions provided in the semiconductor substrate below a second portion of each one of the assist gates opposite from the first portion, the drain regions adjacent to a second one of the substantially U-shaped recesses,
wherein channel regions are formed under a third portion of each of the assist gates between the source regions and the drain regions.
2. The semiconductor device as claimed in claim 1 , wherein the tunnel oxide film has a thickness equal to or greater than 4 nm.
3. The semiconductor device as claimed in claim 1 , wherein the tunnel oxide film has a thickness equal to or greater than 5 nm.
4. The semiconductor device as claimed in claim 1 , wherein the tunnel oxide film has a thickness equal to or greater than 6 nm.
5. The semiconductor device as claimed in claim 1 , wherein the tunnel oxide film has a thickness equal to or greater than 7 nm.
6. The semiconductor device as claimed in claim 1 , wherein the tunnel oxide film has a thickness equal to or greater than 10 nm.
7. The semiconductor device as claimed in claim 1 , wherein the charge storage region includes a top oxide film provided on the storage film, and at least one of the tunnel oxide film and the top oxide film has a thickness equal to or greater than 4 nm.
8. The semiconductor device as claimed in claim 1 , wherein the charge storage region includes a top oxide film provided on the storage film, and at least one of the tunnel oxide film and the top oxide film has a thickness equal to or greater than 5 nm.
9. The semiconductor device as claimed in claim 1 , wherein the charge storage region includes a top oxide film provided on the storage film, and at least one of the tunnel oxide film and the top oxide film has a thickness equal to or greater than 6 nm.
10. The semiconductor device as claimed in claim 1 , wherein the charge storage region includes a top oxide film provided on the storage film, and at least one of the tunnel oxide film and the top oxide film has a thickness equal to or greater than 7 nm.
11. The semiconductor device claimed in claim 1 , wherein the charge storage region includes a top oxide film provided on the storage film, and at least one of the tunnel oxide film and the top oxide film has a thickness equal to or greater than 10 nm.
12. The semiconductor device claimed in claim 1 , wherein the tunnel oxide film has a thickness in which FN tunneling is dominant.
13. The semiconductor device as claimed in claim 1 , further comprising sidewalls provided along sides of the assist gates.
14. The semiconductor device as claimed in claim 13 , wherein the sidewalls are part of the charge storage region provided along the sides of the assist gates.
15. The semiconductor device as claimed in claim 1 , wherein the charge storage region is located below the assist gates.
16. The semiconductor device as claimed in claim 1 , wherein the tunnel oxide film includes a gate insulating film provided below the assist gates.
17. The semiconductor device as claimed in claim 1 , wherein the charge storage region is provided so as to cover the assist gates.