Semiconductor device
A semiconductor element is configured to prevent deterioration thereof due to an electrical charge occurring at a top surface/bottom surface of a support substrate during a plasma process in manufacturing a semiconductor device using an SOI substrate. The semiconductor device includes a MOS transistor formed on an SOI layer of the SOI substrate; a wiring pattern which is formed on an interlayer insulating film covering the SOI layer and is connected to a gate electrode or a diffusion layer of the MOS transistor through a via; and a protection circuit which is connected between the support substrate of the SOI substrate and the wiring pattern and which, when the amount of charges generated with respect to the gate electrode during a plasma process of forming the wiring pattern exceeds a predetermined value, discharges the charges toward the support substrate or blocks the charges. For example, the protection circuit includes a series circuit of a PN junction diode and an NP junction diode each having a breakdown voltage value corresponding to the predetermined value.
1 . A semiconductor device comprising:
a semiconductor element having a diffusion layer and a gate electrode with a gate insulating film interposed therebetween, the diffusion layer being formed within a silicon layer of an SOI substrate in which the silicon layer is formed on a support substrate with an insulating film interposed therebetween;
a wiring pattern which is formed on an interlayer insulating film covering the silicon layer and is connected to the gate electrode or the diffusion layer of the semiconductor element through a via hole (hereinafter, referred to as ‘via’) penetrating the interlayer insulating film; and
a protection circuit which is connected between the support substrate and the wiring pattern connected to the gate electrode or the diffusion layer and which, when the amount of charges generated with respect to the gate electrode during a plasma process of forming the wiring pattern exceeds a predetermined value, discharges the charges toward the support substrate or blocks the charges.
2 . The semiconductor device according to claim 1 ,
wherein the protection circuit includes a series circuit of a PN junction diode and an NP junction diode each having a breakdown voltage value corresponding to the predetermined value.
3 . The semiconductor device according to claim 1 ,
wherein the protection circuit includes a PNP junction device or an NPN junction device having a breakdown voltage value corresponding to the predetermined value.
4 . The semiconductor device according to claim 2 ,
wherein one of the PN junction diode and the NP junction diode is formed within the silicon layer, and
the other one of the PN junction diode and the NP junction diode is formed by a first conduction-type semiconductor substrate composed of the support substrate and a second conduction-type impurity diffusion layer which is formed within the semiconductor substrate and has a polarity reverse to that of the first conduction-type semiconductor substrate.
5 . A semiconductor device comprising:
a semiconductor element having a diffusion layer and a gate electrode with a gate insulating film interposed therebetween, the diffusion layer being formed within a silicon layer of an SOI substrate in which the silicon layer is formed on a support substrate with an insulating film interposed therebetween;
a wiring pattern which is formed on an interlayer insulating film covering the silicon layer and is connected to the gate electrode or the diffusion layer of the semiconductor element through a first via penetrating the interlayer insulating film;
a protection circuit which is connected between the support substrate and the wiring pattern connected to the gate electrode or the diffusion layer and which, when the amount of charges generated with respect to the gate electrode during a plasma process of forming the wiring pattern exceeds a predetermined value, discharges the charges toward the support substrate; and
a dummy conductive pattern which is formed on the interlayer insulating film and is connected to the support substrate through a second via penetrating the interlayer insulating film.
6 . The semiconductor device according to claim 5 ,
wherein the dummy conductive pattern is formed by using one of a plural-dot-shaped conductive pattern, a plate-shaped conductive pattern, and a line-shaped conductive pattern or by a combination of the plural-dot-shaped conductive pattern, the plate-shaped conductive pattern, and the line-shaped conductive pattern.
7 . The semiconductor device according to claim 1 ,
wherein the semiconductor element is a field effect transistor.
8 . The semiconductor device according to claim 2 ,
wherein the semiconductor element is a field effect transistor.
9 . The semiconductor device according to claim 3 ,
wherein the semiconductor element is a field effect transistor.
10 . The semiconductor device according to claim 4 ,
wherein the semiconductor element is a field effect transistor.
11 . The semiconductor device according to claim 5 ,
wherein the semiconductor element is a field effect transistor.
12 . The semiconductor device according to claim 6 ,
wherein the semiconductor element is a field effect transistor.