Granted Patent B1

US 7,816,203 · App. 11/378,464 · Granted Oct 19, 2010

Abstract

Claims (41)

1. A method for fabricating a semiconductor device overlying a semiconductor substrate, the method comprising the steps of:

forming an oxide-nitride-oxide (ONO) gate insulator stack overlying the substrate;

depositing a gate electrode overlying the ONO gate insulator stack;

depositing a layer of insulating material overlying the gate electrode;

depositing a layer of spin on glass overlying and in contact with the layer of insulating material, the layer of spin on glass having a surface and comprising a substantially ultraviolet opaque material;

etching a trench into the layer of spin on glass;

depositing a layer of copper overlying the surface of the layer of spin on glass and filling the trench; and

removing the layer of copper overlying the surface of the layer of spin on glass.

2. The method of claim 1 further comprising the step of heating the layer of spin on glass to a temperature between about 350° C. and 450° C. prior to the step of etching a trench.

3. The method of claim 2 further comprising the steps of:

depositing a dielectric layer overlying the layer of copper filling the trench;

etching an opening through the dielectric layer to expose a portion of the layer of copper filling the trench; and

depositing a second layer of copper filling the opening and electrically contacting the portion of the layer of copper filling the trench.

4. The method of claim 3 wherein all steps subsequent to the step of heating the layer of spin on glass are conducted at temperatures less than 450° C.

5. A method for fabricating a semiconductor device in and overlying a semiconductor substrate, the method comprising the steps of:

forming a gate dielectric layer overlying the semiconductor substrate;

depositing a silicon nitride layer overlying the gate dielectric layer;

forming a silicon oxide layer overlying the silicon nitride layer;

depositing a polycrystalline silicon layer overlying the silicon oxide layer;

patterning the polycrystalline silicon layer, silicon oxide layer and silicon nitride layer to form a gate stack;

ion implanting conductivity determining dopant ions to form a source region and a drain region self aligned to the gate stack;

depositing a planarized insulating layer overlying the gate stack, the source region and the drain region;

etching contact openings in the planarized insulating layer to expose a portion of the source region and a portion of the drain region;

forming conductive plugs in the contact openings electrically contacting the source region and the drain region respectively;

depositing a spin on glass layer overlying the gate stack, the source region and the drain region, the spin on glass layer having an upper surface and comprising a substantially ultraviolet opaque material; and

etching openings through the spin on glass layer to align with the conductive plugs.

6. The method of claim 5 further comprising the step of densifying the spin on glass layer by heating to a temperature between about 350° C. and about 450° C. prior to the step of etching openings.

7. The method of claim 5 further comprising the step of depositing a second insulating layer in contact with the upper surface of the layer of spin on glass.

8. The method of claim 5 further comprising the step of chemical vapor depositing a layer of silicon oxide in contact with the upper surface of the layer of spin on glass.

9. The method of claim 5 wherein the planarized insulating layer is deposited by a low pressure chemical vapor deposition process overlying the gate stack, the source region and the drain region prior to the step of depositing a spin on glass layer.

10. A method for fabricating a semiconductor device overlying a semiconductor substrate, the method comprising the steps of:

forming an oxide-nitride-oxide (ONO) gate insulator stack overlying the substrate;

depositing a gate electrode overlying the ONO gate insulator stack;

depositing a first layer of insulating material overlying the gate electrode;

depositing a layer of spin on glass overlying and in contact with the first layer of insulating material, the layer of spin on glass having a surface and comprising a substantially ultraviolet opaque material;

heating the layer of spin on glass to a temperature between about 350° C. and 450° C.; and

limiting all subsequent process steps to temperatures less than 450° C.

11. The method of claim 10 further comprising the step of chemical vapor depositing a second layer of insulating material overlying the layer of spin on glass.

12. The method of claim 10 further comprising the steps of:

etching a trench extending into the layer of spin on glass; and

filling the trench with a metal comprising copper, wherein the metal is electrically contacting the gate electrode.

Assignments (8)