Conductive hard mask to protect patterned features during trench etch
View Patent ↗A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.
1. A method for forming a semiconductor device, the method comprising:
depositing a layer of semiconductor material;
depositing a first conductive layer or layerstack above the semiconductor material;
patterning and etching the first conductive layer or layerstack and the semiconductor material into first pillars in a single photolithography step;
depositing a dielectric layer above the first pillars; and
etching trenches in the dielectric layer, wherein a portion of the first conductive layer or layerstack is exposed in the trenches,
wherein the semiconductor material is not exposed in the trenches,
wherein the pillars do not include a resistivity-switching binary metal oxide or nitride; and
wherein the pillars are etched to have a pillar width, the trenches are etched to have a trench width, and the trench width is at least as wide as the pillar width.
2. The method of claim 1 further comprising forming top conductors by filling the trenches with second conductive material and planarizing to remove overfill of the second conductive material.
3. The method of claim 2 wherein the top conductors comprise tungsten, copper, or aluminum.
4. The method of claim 1 wherein the step of depositing a layer of semiconductor material comprises:
depositing a bottom heavily doped region of a first conductivity type;
depositing an undoped or lightly doped middle region above and in contact with the bottom heavily doped region.
5. The method of claim 4 wherein the step of depositing a layer of semiconductor material further comprises depositing a top heavily doped region of a second conductivity type above and in contact with the undoped or lightly doped middle region, the second conductivity type opposite the first, the top heavily doped region doped by in situ doping.
6. The method of claim 4 wherein the step of depositing a layer of semiconductor material further comprises forming a top heavily doped region of a second conductivity type by doping a top portion of the middle undoped or lightly doped region by ion implantation, the second conductivity type opposite the first.
7. The method of claim 1 wherein the semiconductor material is silicon, germanium, or an alloy of silicon and/or germanium.
8. The method of claim 7 wherein the semiconductor material is silicon.
9. The method of claim 7 wherein, in the completed device, the semiconductor material is polycrystalline.
10. The method of claim 1 wherein each of the first pillars comprises a vertically oriented diode.
11. The method of claim 10 wherein each diode is a semiconductor junction diode.
12. The method of claim 11 wherein each semiconductor junction diode is a p-i-n diode.
13. The method of claim 1 further comprising, before the step of depositing the first conductive layer or layerstack above the semiconductor material, forming a dielectric rupture antifuse layer on and in contact with the layer of semiconductor material.
14. The method of claim 13 wherein the dielectric rupture antifuse comprises silicon dioxide.
15. The method of claim 1 wherein the first conductive layer or layerstack comprises a metal or metal alloy.
16. The method of claim 15 wherein the metal or metal alloy is tungsten or a tungsten alloy.
17. The method of claim 16 wherein the tungsten or tungsten alloy is sputtered tungsten.