IP Library Granted Patent US 7,606,085
Granted Patent B2
US 7,606,085 · App. 11/501,449 · Granted Oct 20, 2009

Semiconductor device and control method of the same

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Quick Facts
Patent No.
US 7,606,085
App. No.
11/501,449
Granted
Oct 20, 2009
Kind
B2
Abstract

The present invention is a semiconductor device including: a resistor R 11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N 11 provided between the resistor R 11 and FET 15 and used for outputting a reference voltage; a feedback node N 12 provided between the power supply Vcc and the ground; and a voltage control circuit ( 19 ) that maintains a voltage of the feedback node N 12 at a constant level by using the reference voltage of the output node N 11 and the voltage of the feedback node N 12 . The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

Claims (29)

1. A semiconductor device comprising:

first and second resistor parts connected in series between a first power supply and a second power supply;

an output node provided between the first and second resistor parts, a reference voltage being output via the output node;

a feedback node provided between the first power supply and the first resistor part; and

a voltage control circuit that maintains a voltage of the feedback node at a constant level by using the reference voltage of the output node and the voltage of the feedback node, wherein the voltage control circuit comprises a differential amplifier circuit that receives the reference voltage of the output node and the voltage of the feedback node, and a current control circuit that controls a current flowing between the first power supply and the feedback node by using an output of the differential amplifier circuit, wherein the current control circuit includes an FET having a gate connected to the output of the differential amplifier circuit and a source and a drain connected to the first power supply and the feedback node, respectively.

2. The semiconductor device as claimed in claim 1 , wherein the voltage of the feedback node is divided with a voltage ratio of the output node and the feedback node, and a divided voltage is applied to the differential amplifier circuit.

3. The semiconductor device as claimed in claim 1 , wherein the second resistor part is a diode having a forward direction from the output node to the second power supply.

4. The semiconductor device as claimed in claim 1 , wherein the first resistor part is made of polysilicon and has a temperature coefficient of current approximately equal to that of the second resistor part.

5. A semiconductor device comprising:

first and second resistor parts connected in series between a first power supply and a second power supply;

an output node provided between the first and second resistor parts a reference voltage being output via the output node;

a feedback node provided between the first power supply and the first resistor part;

a voltage control circuit that maintains a voltage of the feedback node at a constant level by using the reference voltage of the output node and the voltage of the feedback node;

a memory cell connected to the output node;

a voltage generating circuit that generates a voltage applied to the memory cell by using the reference voltage, wherein the reference voltage is used for reading data from the memory cell; and

a switch that is coupled with the output node and causes the reference voltage to be generated in response to a change of an address that specifies the memory cell.

6. The semiconductor device as claimed in claim 5 , wherein the voltage of the feedback node is divided with a voltage ratio of the output node and the feedback node, and a divided voltage is applied to the differential amplifier circuit.

7. The semiconductor device as claimed in claim 5 , wherein the second resistor part is a diode having a forward direction from the output node to the second power supply.

8. The method as claimed in claim 7 , further comprising:

programming the memory cell using the reference voltage; and

erasing the memory cell using the reference voltage.

9. The semiconductor device as claimed in claim 5 , wherein the first resistor part is made of polysilicon and has a temperature coefficient of current approximately equal to that of the second resistor part.

10. The semiconductor device as claimed in claim 5 , wherein the reference voltage is used for programming and erasing the memory cell.

11. A method of controlling a semiconductor device equipped with first and second resistor parts connected in series between a first power supply and a second power supply; an output node provided between the first and second resistor parts, a reference voltage being output via the output node; and a feedback node provided between the first power supply and the first resistor part, the method comprising the steps of:

maintaining a voltage of the feedback node at a constant level by using the reference voltage of the output node and the voltage of the feedback node;

outputting the reference voltage via the output node;

generating a voltage applied to a memory cell using the reference voltage;

reading data from the memory cell using the reference voltage; and

generating the reference voltage in response to a change of address that specifies the memory cell.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036044/0122 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2006
From: WADA, HIROAKI; KURIHARA, KAZUHIRO
To: SPANSION LLC.
Reel/Frame 018289/0673 →