Antifuse one time programmable memory array and method of manufacture
View Patent ↗A method for making a one time programmable (OTP) memory array includes providing a wafer comprising a buried insulator layer and a semiconductor layer over the buried insulator layer and forming a plurality of bit lines in the semiconductor layer. Each of the plurality of bit lines comprise a portion of the semiconductor layer and the plurality of bit lines are separated from each other by isolation regions formed in the semiconductor layer. The method further includes forming an anti-fuse dielectric layer over and in physical contact with the plurality of bit lines and the isolation regions, and forming a plurality of word lines over and in physical contact with the anti-fuse dielectric layer.
1. A method for making a one time programmable (OTP) memory array, the method comprising:
providing a wafer comprising a buried insulator layer and a semiconductor layer on and in physical contact with the buried insulator layer;
forming a plurality of bit lines in the semiconductor layer in physical contact with the buried insulator layer, wherein each of the plurality of bit lines comprise a portion of the semiconductor layer and the plurality of bit lines are separated from each other by isolation regions formed in the semiconductor layer and also in physical contact with the buried insulator layer;
forming an anti-fuse dielectric layer over and in physical contact with the plurality of bit lines and the isolation regions; and
forming a plurality of word lines over and in physical contact with the anti-fuse dielectric layer.
2. The method of claim 1 , wherein forming the plurality of bit lines in the semiconductor layer comprises:
forming isolation trenches in the semiconductor layer; and
filling the isolation trenches with an insulating material.
3. The method of claim 2 , further comprising implanting an implant having a first conductivity type into the semiconductor layer prior to forming the isolation trenches.
4. The method of claim 3 , wherein the plurality of word lines are implanted with an implant having a second conductivity type, different from the first conductivity type.
5. The method of claim 1 , further comprising implanting an implant having a first conductivity type into the plurality of bit lines.
6. The method of claim 5 , wherein the plurality of word lines are implanted with an implant having a second conductivity type, different from the first conductivity type.
7. The method of claim 1 , wherein the semiconductor layer comprises monocrystalline silicon.
8. The method of claim 1 , wherein each of the plurality of word lines comprise polycrystalline silicon.
9. The method of claim 1 , wherein forming the plurality of word lines comprises:
forming a conductive layer over and in physical contact with anti-fuse dielectric layer; and
patterning the conductive layer to form the plurality of word lines.
10. The method of claim 8 , further comprising forming a sidewall spacer adjacent each word line.
11. The method of claim 1 , wherein the plurality of word lines lie substantially perpendicular in reference to the plurality of bit lines and wherein a unit cell of the OTP memory array is defined at each crossing of a word line of the plurality of word lines over a bit line of the plurality of bit lines.
12. A method for making a one time programmable (OTP) memory array, the method comprising:
providing a silicon-on-insulator (SOI) wafer, the SOI wafer comprising a support substrate, a buried oxide layer over and in physical contact with the support substrate, and a monocrystalline silicon layer over and in physical contact with the buried oxide layer;
forming a plurality of isolation trenches in the monocrystalline silicon layer of the SOI wafer and extending down to the buried oxide layer;
filling the plurality of isolation trenches with an isolation material that is in physical contact with the buried oxide layer to form a plurality of isolation regions in the monocrystalline silicon layer of the SOI wafer, wherein regions of the monocrystalline silicon layer of the SOI wafer remaining between the plurality of isolation trenches define a plurality of bit lines of the OTP memory array;
forming an anti-fuse dielectric layer over and directly contacting the plurality of bit lines and the plurality of isolation regions; and
forming a plurality of word lines over and directly contacting the anti-fuse dielectric layer, wherein the plurality of word lines lie substantially perpendicular in reference to the plurality of bit lines and wherein a unit cell of the OTP memory array is defined at each crossing of a word line of the plurality of word lines over a bit line of the plurality of bit lines.
13. The method of claim 12 , wherein forming the plurality of word lines over and directly contacting the anti-fuse dielectric layer comprises:
forming a conductive layer over and directly contacting the anti-fuse dielectric layer; and
patterning the conductive layer to form the plurality of word lines.
14. The method of claim 13 , wherein the conductive layer comprises polycrystalline silicon.
15. The method of claim 12 , wherein the plurality of bit lines are doped with a p-type implant and the plurality of word lines are doped with an n-type implant.
16. The method of claim 12 , wherein the anti-fuse dielectric layer comprises a material selected from a group consisting of an oxide, a nitride, and amorphous silicon.
17. A method for making a one time programmable (OTP) memory array, comprising:
providing a support substrate;
forming a buried insulator layer over and in physical contact with the support substrate;
forming a plurality of bit lines over and in physical contact with the buried insulator layer, wherein the plurality of bit lines are separated from each other by isolation regions in physical contact with the buried insulator layer;
forming an anti-fuse dielectric layer over and in physical contact with the plurality of bit lines and the isolation regions; and
forming a plurality of word lines over and in physical contact with the anti-fuse dielectric layer, wherein the plurality of word lines lie substantially perpendicular in reference to the plurality of bit lines and wherein a unit cell of the OTP memory array is defined at each crossing of a word line of the plurality of word lines over a bit line of the plurality of bit lines.
18. The method of claim 17 , further comprising:
forming the plurality of bit lines with monocrystalline silicon.
19. The method of claim 17 , further comprising:
forming the plurality of word lines with polycrystalline silicon.
20. The method of claim 17 , further comprising:
doping the plurality of bit lines with an implant having a first conductivity type; and
doping the plurality of word lines with an implant having a second conductivity type, different from the first conductivity type.