Termination structures for super junction devices
View Patent ↗A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12 ; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24 ′ of the second dopant type.
1. A semiconductor device comprising:
a first layer, wherein the first layer has a first dopant type;
a second layer over the first layer;
a third layer over the second layer, wherein the third layer has the first dopant type;
a plurality of first and second semiconductor regions within the third layer, the first semiconductor region having the first dopant type and the second semiconductor region having a second dopant type,
wherein the first and second semiconductor regions are disposed laterally relative to one another in an alternating pattern to form a super junction, and wherein the super junction terminates with a final second semiconductor region of the second dopant type; and
a drain region within the third layer over at least a portion of the first and second semiconductor regions, wherein the drain region extends over only a portion of the final second semiconductor region.
2. The semiconductor device of claim 1 , wherein the final second semiconductor region has a first width and each of the other second semiconductor regions have a second width, and wherein the first width is different from than the second width.
3. The semiconductor device of claim 2 , wherein the first width is approximately half the second width.
4. The semiconductor device of claim 1 , wherein the first dopant type is P-type and the second dopant type is N-type.
5. The semiconductor device of claim 1 , wherein the second layer is an oxide layer.
6. The semiconductor device of claim 1 , wherein the second layer is a buried layer having the second dopant type.
7. The semiconductor device of claim 1 , wherein the third layer surrounds all but one surface of the super junction.
8. A method of manufacturing a semiconductor device comprising:
providing a first layer having a first dopant type;
providing a second layer over the first layer;
providing a third layer over the second layer, the third layer having the first dopant type;
providing a plurality of first and second semiconductor regions within the third layer, the first semiconductor region having the first dopant type and the second semiconductor region having the second dopant type,
wherein the first and second semiconductor regions are disposed laterally relative to one another in an alternating pattern to form a super junction, and wherein the super-junction terminates with a final second semiconductor region of the second dopant type; and
providing a drain region within the third layer over at least a portion of the first and second semiconductor regions, wherein the drain region does not completely extend over the final second semiconductor region.
9. The method of claim 8 , wherein the final second semiconductor region has a first width and the other second semiconductor regions each have a second width, and wherein the first width is less than the second width.
10. The method of claim 8 , wherein the providing the plurality of first and second semiconductor regions within the third layer includes providing the final second semiconductor region with a first width and the other second semiconductor regions with a second width, and wherein the first width is less than the second width.
11. The method of claim 10 , wherein the first width is half the second width.
12. The method of claim 8 , wherein the first dopant type is P-type and the second dopant type is N-type.
13. The method of claim 8 , wherein the step of providing the second layer includes providing an oxide layer.
14. A semiconductor device comprising:
a first layer, wherein the first layer has a first dopant type;
a second layer over the first layer;
a third layer over the second layer, wherein the third layer has the first dopant type; a plurality of first and second semiconductor regions within the third layer, the first semiconductor region having the first dopant type and the second semiconductor region having a second dopant type, wherein the first and second semiconductor regions are disposed laterally relative to one another in an alternating pattern to form a super junction, and wherein the super junction terminates with a final second semiconductor region of the second dopant type; and
a drain region within the third layer over at least a portion of the first and second semiconductor regions, wherein the drain region does not extend over the final second semiconductor region.
15. The semiconductor device of claim 14 , wherein the final second semiconductor region has a first width and each of the other second semiconductor regions have a second width, and wherein the first width is different from than the second width.
16. The semiconductor device of claim 15 , wherein the first width is approximately half the second width.
17. The semiconductor device of claim 14 , wherein the first dopant type is P-type and the second dopant type is N-type.
18. The semiconductor device of claim 14 , wherein the second layer is an oxide layer.
19. The semiconductor device of claim 14 , wherein the second layer is a buried layer having the second dopant type.
20. The semiconductor device of claim 14 , wherein the third layer surrounds all but one surface of the super junction.