Low power content addressable memory
View Patent ↗A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.
1. A method of operation within a content addressable memory (CAM) device, the method comprising:
storing, in a first row of CAM cells, a first value that indicates respective Boolean operations to be performed within each of the CAM cells of the first row;
simultaneously combining respective pairs of operands within the respective CAM cells of the first row according to the respective Boolean operations indicated by the first value to generate a plurality of logic signals; and
generating an output signal in either a first state or a second state according to whether all the plurality of logic signals have the first state.
2. The method of claim 1 further comprising storing, in a second row of CAM cells, a second value that indicates respective Boolean operations to be performed within each of the CAM cells of the second row, wherein the second value is different than the first value.
3. The method of claim 2 further comprising performing the respective Boolean operations indicated by the first value in the first row of CAM cells concurrently with the respective Boolean operations indicated by the second value in the second row of CAM cells.
4. The method of claim 1 wherein the first value comprises a plurality of multi-bit data entities, each of the plurality of multi-bit data entities having a bit pattern that indicates one of the respective Boolean operations.
5. The method of claim 4 wherein a first bit pattern indicates a first Boolean operation and wherein a second bit pattern indicates a second Boolean operation.
6. The method of claim 1 wherein generating an output signal in either a first state or a second state comprises discharging a precharged match line if at least one of the plurality of logic signals is in the second state.
7. The method of claim 1 further comprising providing the respective pairs of operands to the respective CAM cells from two or more multi-bit input values prior to simultaneously combining the respective pairs of operands, each of the two or more multi-bit input values providing a respective operand of the respective pairs of operands.
8. The method of claim 1 further comprising selecting a first mode of operation of the CAM device if a bypass signal is not asserted and selecting a second mode of operation of the CAM device if a bypass signal is asserted.
9. The method of claim 8 further comprising converting the bits of the first value to data state signals if the first mode of operation is selected.
10. The method of claim 8 wherein the first value indicates the respective Boolean operations to be performed within each of the CAM cells of the first row if the second mode of operation is selected.
11. The method of claim 1 wherein each of the plurality of logic signals is either in a first state or a second state according to whether the respective Boolean operations performed on each of the respective pairs of operands evaluates to true or false respectively.