Granted Patent B2

US 7,671,405 · App. 11/646,157 · Granted Mar 2, 2010

Abstract

Claims (48)

1. A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising:

forming two adjacent symmetric dual bit memory cells; each comprising a charge trapping dielectric layer configured to store two bits of data therein, and defining a first bitline opening there between wherein each of the memory cells are symmetrical about a centerline perpendicular to and passing through the charge trapping dielectric layer wherein two bits can be stored within the charge trapping dielectric layer with a bit stored on either side of the centerline approximately equidistant from each other;

forming first polysilicon layer features over the charge trapping dielectric layer;

performing a first bitline implant into the first bitline opening to establish a buried first bitline within the substrate;

forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define a second bitline opening between the adjacent memory cells;

performing a deep arsenic implant into the second bitline opening to establish a second bitline within the substrate that is smaller than the first bit line; and

performing back end processing.

2. The method of claim 1 , wherein the deep arsenic implant energy is about 20-40 keV.

3. The method of claim 1 , wherein the deep arsenic implant is formed to a depth of 70 nanometers or greater.

4. The method of claim 1 , wherein the spacer material is formed to a thickness of 5 nanometers or greater.

5. The method of claim 1 , wherein the spacer is etched to a thickness of about 5 to 30 nanometers.

6. The method of claim 5 , wherein the etching process comprises plasma etching.

7. A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising:

forming two adjacent symmetric dual bit memory cells; each comprising a charge trapping dielectric layer configured to store two bits of data therein, and defining a first bitline opening there between wherein each of the memory cells are symmetrical about a centerline perpendicular to and passing through the charge trapping dielectric layer wherein two bits can be stored within the charge trapping dielectric layer with a bit stored on either side of the centerline approximately equidistant from each other;

forming first polysilicon layer features over the charge trapping dielectric layer;

performing a first bitline implant into the first bitline opening to establish a buried first bitline within the substrate;

forming sidewall spacers adjacent to the polysilicon features thereby defining a second bitline opening;

performing a vertical deep arsenic implant to create a second source/drain the second bitline opening to establish a second bitline within the substrate that is smaller and deeper than the first bitline; and

performing backend processing.

8. The method of claim 7 , wherein the deep arsenic implant energy is about 20-40 keV.

9. The method of claim 7 , wherein the deep arsenic implant is formed to a depth of 70 nanometers or greater.

10. The method of claim 7 , wherein the layer of spacer material is formed to a thickness of 70 nanometers or greater.

11. The method of claim 7 , wherein the first sidewall spacer is etched to a thickness of about 5 to 30 nanometers.

12. The method of claim 7 , wherein the etching comprises plasma etching.

13. The method of claim 7 , wherein the pocket implant is performed at an energy level of around 10 KeV to 40 KeV.

14. The method of claim 7 , wherein the pocket implant is performed at an energy level of around 5 KeV to 30 KeV.

15. The method of claim 7 , wherein the vertical arsenic implant is formed to a depth of about 500 Angstroms.

16. The method of claim 7 , wherein the vertical deep arsenic implant is performed at a dosage of about 1e15/cm2.

17. The method of claim 7 , wherein the second bitlines have a resulting dopant concentration of about 2E20/cm3.

18. The method of claim 7 , wherein the second bitline opening is formed to a width of about 50 nanometers.

19. The method of claim 7 , wherein an optional high temperature oxidation is performed at temperatures between around 700 to 1200 degrees Celsius.

20. The method of claim 7 , wherein a high density plasma oxide deposition to form the layer of spacer material is performed at a temperature of about 300 C to about 700 C under a pressure of about 1-10 mTorr.

21. The method of claim 7 , wherein the pocket implant is performed at an energy level of around 5 KeV to 30 KeV.

22. A communication device, comprising:

a flash memory CPU;

the flash memory operatively coupled to the CPU and configured to transfer data to and from the CPU;

an input component for entering the data;

a display component for displaying information;

a plurality of switches;

flash memory, the flash memory comprising two adjacent symmetric dual bit memory cells formed by the process of;

forming a charge trapping dielectric layer over a substrate;

forming a polysilicon layer over the charge trapping dielectric layer;

forming a hardmask over the polysilicon layer;

patterning the hardmask to form a patterned polysilicon layer and defining a first bitline opening between the two adjacent symmetric dual bit memory cells;

wherein each of the memory cells are symmetrical about a centerline perpendicular to and passing through the charge trapping dielectric layer wherein two bits can be stored within the charge trapping dielectric layer with a bit stored on either side of the centerline approximately equidistant from each other;

performing a vertical arsenic implant to create a source/drain in the first bitline opening;

forming spacer material on sidewalls of the patterned polysilicon to define a second bitline opening that is smaller than the first bitline opening; and

performing a vertical deep arsenic implant into the second bitline opening.

Assignments (9)