Gate replacement with top oxide regrowth for the top oxide improvement
Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
1. A method of replacing a first top oxide over charge storage elements of a memory cell, comprising:
providing a memory cell on a semiconductor substrate and between bit line dielectrics, the memory cell comprising a charge storage layer over the semiconductor substrate and a first poly over the charge storage layer, the charge storage layer comprising two charge storage elements separated by a central dielectric, a first charge storage dielectric material adjacent to and below the charge storage elements, a second charge storage dielectric material adjacent to and above the charge storage elements, and the first to oxide adjacent to and above the second charge storage dielectric material;
removing the entire first poly to expose the first top oxide and the central dielectric;
removing the entire first top oxide to expose the second charge storage dielectric material;
removing an upper portion of the central dielectric and at least a portion of the central dielectric touching side surfaces of the charge storage elements; and
forming a second top oxide on the second charge storage dielectric material.
2. The method of claim 1 , wherein the forming the second top oxide comprises oxidizing a portion of the second charge storage dielectric material.
3. The method of claim 1 , wherein the forming the second top oxide comprises forming a sacrificial layer over the second charge storage dielectric material and converting the sacrificial layer to an oxide layer.
4. The method of claim 3 , wherein the converting the sacrificial layer to the oxide layer comprises a slot plane antenna process.
5. The method of claim 1 , wherein the second top oxide is formed over a remaining portion of the central dielectric, and the side surfaces of the charge storage elements.
6. The method of claim 1 , further comprising forming a second poly over the second top oxide.
7. A method of replacing a first top oxide over charge storage elements of a memory cell, comprising:
providing a memory cell on a semiconductor substrate and between bit line dielectrics, the memory cell comprising a charge storage layer over the semiconductor substrate and a first poly over the charge storage layer, the charge storage layer comprising two charge storage elements separated by a central dielectric, a first charge storage dielectric material adjacent to and below the charge storage elements, a second charge storage dielectric material adjacent to and above the charge storage elements, and the first to oxide adjacent to and above the second charge storage dielectric material;
removing the entire first poly to expose the first top oxide and the central dielectric;
removing the entire first top oxide to expose the second charge storage dielectric material;
removing an upper portion of the central dielectric and at least a portion of the central dielectric touching side surfaces of the charge storage elements; and
oxidizing a portion of the second charge storage dielectric material to form a second top oxide on the second charge storage dielectric material, wherein the second charge storage dielectric material comprises nitride.
8. The method of claim 7 , wherein the oxidizing the portion of the second charge storage dielectric material comprises a slot plane antenna process.
9. A method of replacing a first top oxide over charge storage elements of a memory cell, comprising:
providing a memory cell on a semiconductor substrate and between bit line dielectrics, the memory cell comprising a charge storage layer over the semiconductor substrate and a first poly over the charge storage layer, the charge storage layer comprising two charge storage elements separated by a central dielectric, a first charge storage dielectric material adjacent to and below the charge storage elements, a second charge storage dielectric material adjacent to and above the charge storage elements, and the first to oxide adjacent to and above the second charge storage dielectric material;
removing the entire first poly to expose the first top oxide and the central dielectric;
removing the entire first top oxide to expose the second charge storage dielectric material;
removing an upper portion of the central dielectric and at least a portion of the central dielectric touching side surfaces of the charge storage elements; and
forming a sacrificial layer over the second charge storage dielectric material; and
oxidizing the sacrificial layer to form a second top oxide layer on the second charge storage dielectric material.
10. The method of claim 9 , wherein the oxidizing the sacrificial layer to form the second top oxide comprises a low temperature oxidation process.
11. The method of claim 9 , the oxidizing the sacrificial layer to form the second top oxide comprises a slot plane antenna process.
12. The method of claim 9 , wherein the sacrificial layer comprises silicon nitride, oxide, or combinations thereof.
13. The method of claim 2 , wherein the second charge storage dielectric material comprises siicon rich silicon nitride.
14. The method of claim 2 wherein the oxidizing the second charge storage dielectric material comprises oxidizing the second charge storage dielectric material at about 240 degrees Celsius or more and about 500 degrees Celsius or less.
15. The method of claim 3 , wherein the converting the sacrificial layer to the oxide layer comprises oxidizing the sacrificial layer at about 240 degrees Celsius or more and about 500 degrees Celsius or less.
16. The method of claim 1 , wherein the forming the second top oxide comprises growing the second top oxide in plasma at low temperatures.
17. The method of claim 2 , wherein each of the charge storage elements become thinner in response to the oxidizing the portion of the second charge storage dielectric material.
18. The method of claim 7 , wherein each of the charge storage elements become thinner in response to the oxidizing the portion of the second charge storage dielectric material.
19. The method of claim 7 , wherein the oxidizing the portion of the second charge storage dielectric material comprises a low temperature oxidation process.
20. The method of claim 7 , wherein the oxidizing the portion of the second charge storage dielectric material is performed at a temperature of about 240 degrees Celsius or more and about 500 degrees Celsius or less.