IP Library Granted Patent US 7,633,815
Granted Patent B2
US 7,633,815 · App. 11/951,263 · Granted Dec 15, 2009

Flexible word line boosting across VCC supply

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Quick Facts
Patent No.
US 7,633,815
App. No.
11/951,263
Granted
Dec 15, 2009
Kind
B2
Abstract

Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up table has a list of trim codes that indicates desired boosting ratios. The boosting ratio can vary depending on a level of a supply voltage to provide a sufficient word line voltage, thereby preventing and/or mitigating delay in reading operations. The number of the capacitors in the boosting circuit can be predetermined to be turned on or off according to the trim code. Accordingly, the voltage boost circuit provides a sufficient boosted word line voltage to a core cell gate with flexibility despite fluctuation of the supply voltage level.

Claims (31)

1. A method for producing a boosted voltage for read operations of a memory cell, comprising:

providing a digital code by a VCC comparator according to a level of a supply voltage;

sending the digital code to a look up table;

matching the digital code to a trim code in the look up table; and

commanding a boosting circuit to boost or not to boost the supply voltage according to the trim code.

2. The method of claim 1 , wherein the VCC comparator measures the supply voltage.

3. The method of claim 1 , wherein the VCC comparator encodes the supply voltage.

4. The method of claim 1 , wherein the VCC comparator translates the supply voltage to the digital code.

5. The method of claim 1 , wherein the digital code from the VCC comparator comprises n bits and the digital code is determined by the level of the supply voltage.

6. The method of claim 1 , wherein the digital code is used as a pointer to access a set of trim codes stored in the look up table.

7. The method of claim 1 , wherein the digital code is matched to the one of the trim codes in the look up table.

8. The method of claim 1 , wherein the trim code indicates a boosting ratio which varies depending on the level of the supply voltage.

9. The method of claim 1 , wherein the boosting ratios determine boosting capacitors settings in a boosting circuit.

10. The method claim 1 , wherein commanding the boosting circuit comprises turning on a predetermined set of boosting capacitors according to the trim code.

11. The method of claim 1 , wherein the boosting circuit receives a command whether boost or not to boost the supply voltage based on the trim code.

12. The method of claim 8 , wherein the boosting circuit produces a boosted voltage according to the desired boosting ratio.

13. The method of claim 1 , further comprising using the boosted voltage as a boosted word line voltage for read mode operations of memory cells.

14. The method of claim 1 , further comprising the boosted voltage to the core cell gate.

15. A system for producing a boosted voltage in a memory device, comprising:

a VCC comparator that translates a supply voltage to a digital code;

a look up table that matches the digital code to a trim code; and

a boosting circuit that boosts the supply voltage according to the trim code.

16. The system of claim 15 , wherein the digital code of the VCC comparator is a binary signal.

17. The system of claim 15 , wherein the digital code comprises a set of digital number of 1 or 0.

18. The system of claim 15 , wherein the look up table comprises a list of trim codes.

19. The system of claim 15 , wherein the boosting circuit comprises a set of boosting capacitors.

20. A system that produces a boosted voltage, comprising:

means for translating a level of a supply voltage to a digital code;

means for sending the digital code to a look up table;

means for matching the digital code to a trim code; and

means for commanding a boosting circuit to boost or not to boost the supply voltage based on the trim code.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036049/0581 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2007
From: CH'NG, CHIN-GHEE; CH'NG, SHEAU-YANG
To: SPANSION LLC
Reel/Frame 020256/0687 →