Non-volatile memory device and methods of using
View Patent ↗The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.
1. A method comprising:
adjusting a voltage threshold of a first select gate of a first NAND string electrically connected to a first bit line, the first NAND string comprising a plurality of NAND storage gates including two outer NAND storage gates, NAND[ 0 ] and NAND[N], and a plurality of inner NAND storage gates, N[ 1 ]-N[N− 1 ], between the two outer NAND storage gates, where NAND[ 0 ] is the outer NAND storage gate of the NAND string most closely coupled to the first bit line and NAND[N] is the outer NAND storage gate of the NAND string least closely coupled to the first bit line, and wherein NAND[ 0 ] is coupled in series between the first select gate and an interior NAND storage gate, NAND[I], where I is an integer between 1 and N− 1 , and wherein adjusting comprises one of adjusting the voltage threshold by increasing a relative number of primary carriers at a charge storage location of the first select gate, or decreasing the relative number of primary carriers.
2. The method of claim 1 wherein adjusting comprises increasing the relative number of primary carriers.
3. The method of claim 2 , wherein electrons are the primary charge carrier.
4. The method of claim 1 wherein adjusting comprises decreasing the relative number of primary carriers.
5. The method of claim 4 , wherein electrons are the primary charge carrier.
6. The method of claim 1 further comprising simultaneously adjusting at the same time as the Vt of the first select gate a voltage threshold of a second select gate of the first NAND string by increasing the relative number of primary carriers at a charge storage location of the second select gate, wherein the primary carriers are of the type used to erase the storage gate NAND[ 0 ], and NAND[N] is coupled in series between the second select gate and the interior NAND storage gate.
7. The method of claim 1 comprising simultaneously adjusting at the same time as the voltage threshold of the first select gate a voltage threshold of a second select gate of the first NAND string, wherein NAND[N] is coupled in series between the second select gate and the interior NAND storage gate.
8. The method of claim 2 , wherein holes are the primary charge carrier.
9. The method of claim 4 , wherein holes are the primary charge carrier.
10. The method of claim 1 further comprising:
providing a read voltage to a control electrode of the first select gate of a NAND string;
determining a logic state of the first select gate based on the read voltage; and
in response to the logic state not matching an expected logic state
adjusting, in response to the logic state not matching an expected logic state, a voltage threshold of a first select gate of a first NAND string electrically connected to a first bit line, the first NAND string comprising a plurality of NAND storage gates including two outer NAND storage gates, NAND[ 0 ] and NAND[N], and a plurality of inner NAND storage gates, N[ 1 ]-N[N− 1 ], between the two outer NAND storage gates, where NAND[ 0 ] is the outer NAND storage gate of the NAND string most closely coupled to the first bit line and NAND[N] is the outer NAND storage gate of the NAND string least closely coupled to the first bit line, and wherein NAND[ 0 ] is coupled in series between the first select gate and an interior NAND storage gate, NAND[I], where I is an integer between 1 and N− 1 .
11. The method of claim 10 further comprising:
repeating providing, determining and adjusting the voltage threshold until the logic state matches the expected logic state.
12. The method of claim 10 wherein providing and determining are repeated to determine a voltage threshold value of the first select gate, and adjusting the voltage threshold includes adjusting the voltage threshold in response to the voltage threshold value being outside an expected range.
13. The method of claim 10 wherein adjusting comprises adjusting the voltage threshold of the first select gate to be closer to ground.
14. The method of claim 10 wherein adjusting comprises adjusting the voltage threshold of the first select gate to be further from ground.
15. The method of claim 10 wherein adjusting comprises adjusting the voltage threshold by increasing a relative number of primary carriers at a charge storage location of the first select gate.
16. The method of claim 10 wherein adjusting comprises adjusting the voltage threshold by decreasing a relative number of primary carriers at a charge storage location of the first select gate.
17. The method of claim 10 wherein NAND[ 0 ] is coupled in series between the first select gate and the interior NAND storage gate.
18. The method of claim 10 wherein NAND[N] is coupled in series between the first select gate and the interior NAND storage gate.
19. A method comprising:
adjusting a voltage threshold of a first select gate of a first NAND electrically connected to a first bit line, the first NAND string comprising a plurality of NAND storage gates including two outer NAND storage gates, NAND[ 0 ] and NAND[N], and a plurality of inner NAND storage gates, N[ 1 ]-N[N− 1 ], between the two outer NAND storage gates, where NAND[ 0 ] is the outer NAND storage gate of the NAND string most closely coupled to the first bit line and NAND[N] is the outer NAND storage gate of the NAND string least closely coupled to the first bit line, and wherein NAND[ 0 ]is coupled in series between the first select gate and an interior NAND storage gate, NAND[I], where I is an integer between 1 and N− 1 .
20. A method comprising:
adjusting a voltage threshold of a first select gate of a first NAND string connected to one of a first bit line or a common source line, the first NAND string comprising a plurality of NAND storage gates including two outer NAND storage gates, NAND[ 0 ] and NAND[N], and a plurality of inner NAND storage gates, N[ 1 ]-N[N− 1 ], between the two outer NAND storage gates, where NAND[ 0 ] is the outer NAND storage gate of the NAND string most closely coupled to the first bit line and NAND[N] is the outer NAND storage gate of the NAND string least closely coupled to the first bit line, and wherein one of the two outer NAND storage gates is coupled in series between the first select gate and an interior NAND storage gate, NAND[I], where I is an integer between 1 and N− 1 .