Automated method and apparatus for very early validation of chip power distribution networks in semiconductor chip designs

1. An automated method of generating a semiconductor chip layout including validating a chip-level physical power distribution network to produce a corrected chip power grid, comprising:

performing, by a computer, a plurality of checks dispersed through a final chip design process for detecting and correcting power connection problems as an integral part of a chip designing process by:

using coded connectivity attributes in a chip power grid and a chip floor plan for a chip design to speed up a checking process;

analyzing a full-chip power distribution network against circuit abstracts in the chip floor plan in place of actual circuit layouts for chips; and

checking each power metal level in the network in succession against a power level above and/or below without building a complete logical representation of chip power metallurgy and via structure.

2. The method of claim 1 , further comprising:

containing net connectivity for all power metals in the chip power grid;

containing circuit abstracts and net connectivity for all circuit pins in the chip floor plan; and

modeling internal power and metal images using metal pin and blockage shapes in the circuit abstracts.

3. The method of claim 2 , further comprising:

finding power shorts, which are metals in a full-chip power grid of a same level but of different power connectivity intersecting with each other;

finding floating power metals, which are metals in the full-chip power grid that do not intersect with any power metal or circuit power pin from either above or below and that are not connected to any circuit's power pin through a power wire extension existing in the full-chip power grid;

finding power antennas, which are metals in the full-chip power grid that intersect only with a power metal or a power pin of a different power domain from above or below, so that no connection can be made;

finding macro power shorts, which are metals in the full-chip power grid that intersect a circuit abstract's metal blockage shape or an abstract's pin shape of different connectivity; and

finding macro power opens, which are macros placed in the chip floor plan, but that are disconnected from the full-chip power grid because its highest level of power pins does not intersect with any power metal of a next higher level or any power wire extension of the same level in the chip power grid.

4. The method of claim 3 , wherein finding power opens and finding power shorts are executable independently and separately to any number of metal levels and power domains by providing explicit input specifications to one or more of:

a specific power metal layer to be checked;

a specific power net name to be checked; and

specific upper and lower metal layer names to be checked against a power metal-under-test.

5. The method of claim 4 , further comprising:

performing post design checks after a final chip layout has been generated.

6. The method of claim 5 , further comprising:

feeding back errors detected by any mentioned check including post design checks for correction and checking.

7. The method of claim 1 , further comprising:

finding power shorts, which are metals in a full-chip power grid of a same level but of different power connectivity intersecting with each other;

finding floating power metals, which are metals in the full-chip power grid that do not intersect with any power metal or circuit power pin from either above or below and that are not connected to any circuits's power pin through a power wire extension existing in the full-chip power grid;

finding power antennas, which are metals in the full-chip power grid that intersect only with a power metal or a power pin of a different power domain from above or below, so that no connection can be made;

finding macro power shorts, which are metals in the full-chip power grid that intersect a circuit abstract's metal blockage shape or an abstract's pin shape of different connectivity; and

finding macro power opens, which are macros placed in the chip floor plan, but that are disconnected from the full-chip power grid because its highest level of power pins does not intersect with any power metal of a next higher level or any power wire extension of the same level in the chip power grid.

8. The method of claim 7 , wherein finding power opens and finding power shorts are executed independently and separately to any number of metal levels and power domains by providing explicit input specifications to one or more of:

a specific power metal layer to be checked;

a specific power net name to be checked; and

specific upper and lower metal layer names to be checked against a power metal-under-test.

9. The method of claim 1 , further comprising:

performing post design checks after a final chip layout has been generated.

10. The method of claim 9 , further comprising:

feeding back errors detected by any mentioned check including post design checks for correction and checking.

11. A computer program product having a program embodied on a non-transitory computer useable medium which, when executed by a computer, causes the computer to implement an automated method for validating a chip-level physical power distribution network for a semiconductor chip to produce a corrected chip power grid by detecting and correcting power connection problems during a chip design process and as an integral part of a chip power routing process, comprising:

code for using coded connectivity attributes in a chip power grid and a chip floor plan for a chip design to speed up a checking process;

code for analyzing a full-chip power distribution network against a chip floor plan containing circuit abstracts in place of actual circuit layouts; and

code for checking each power metal level in succession against a power level above and/or below without building a complete logical representation of chip power metallurgy and via structure.

12. The computer program product of claim 11 , further comprising:

code for containing net connectivity for all power metals in the chip power grid;

code for containing circuit abstracts and net connectivity for all circuit pins in the chip floor plan; and

code for modeling internal power and metal images using metal pin and blockage shapes in the circuit abstracts.

13. The computer program product of claim 12 , further comprising:

code for finding power shorts, which are metals in a full-chip power grid of a same level but of different power connectivity intersecting with each other;

code for finding power metals, which are metals in the full-chip power grid that do not intersect with any power metal or circuit power pin from either above or below and that are not connected to any circuit's power pin through a power wire extension existing in the full-chip power grid;

code for finding power antennas, which are metals in the full-chip power grid that intersect only with a power metal or a power pin of a different power domain from above or below, so that no connection can be made;

code for finding macro power shorts, which are metals in the full-chip power grid that intersect a circuit abstract's metal blockage shape or an abstract's pin shape of different connectivity; and

code for finding macro power opens, which are macros placed in the chip floor plan, but that are disconnected from the full-chip power grid because its highest level of power pins does not intersect with any power metal of a next higher level or any power wire extension of the same level in the chip power grid.

14. The computer program product of claim 13 , wherein code for finding power opens and code for finding power shorts are executable independently and separately to any number of metal levels and power domains by providing explicit input specifications to one or more of:

a specific power metal layer to be checked;

a specific power net name to be checked; and

specific upper and lower metal layer names to be checked against a power metal-under-test.

15. The computer program product of claim 14 , further comprising:

code for performing post design checks after a final chip layout has been generated.

16. The computer program product of claim 15 , further comprising:

code for feeding back errors detected by a mentioned check including post design checks for correction and checking.

17. The computer program product of claim 11 , further comprising:

code for finding power shorts, which are metals in a full-chip power grid of a same level but of different power connectivity intersecting with each other;

code for finding power metals, which are metals in the full-chip power grid that do not intersect with any power metal or circuit power pin from either above or below and that are not connected to any circuit's power pin through a power wire extension existing in the full-chip power grid;

code for finding power antennas, which are metals in the full-chip power grid that intersect only with a power metal or a power pin of a different power domain from above or below, so that no connection can be made;

code for finding macro power shorts, which are metals in the full-chip power grid that intersect a circuit abstract's metal blockage shape or an abstract's pin shape of different connectivity; and

code for finding macro power opens, which are macros placed in the chip floor plan, but that are disconnected from the full-chip power grid because its highest level of power pins does not intersect with any power metal of a next higher level or any power wire extension of the same level in the chip power grid.

18. The computer program product of claim 17 , wherein code for finding power opens and code for finding power shorts are executable independently and separately to any number of metal levels and power domains by providing explicit input specifications to one or more of:

a specific power metal layer to be checked;

a specific power net name to be checked; and

specific upper and lower metal layer names to be checked against a power metal-under-test.

19. The computer program product of claim 11 , further comprising:

code for performing post design checks after a final chip layout has been generated.

20. The computer program product of claim 19 , further comprising:

code for feeding back errors detected by any mentioned check including post design checks for correction and checking.