Method of accurate prediction of electrostatic discharge (ESD) performance in multi-voltage environment
The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to predictive, pre-fabrication methodologies for determining inefficiencies in an integrated circuit (IC) design. The present invention, in one or more implementations, provides an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The method of the present invention yields predictive results that have been comparatively tested.
1. A method of predicting effectiveness of an electrostatic discharge (ESD) circuit using a program simulator and an ESD model, comprising:
populating characteristics of the ESD model and an associated semiconductor device into the program simulator,
determining a minimum current threshold for the ESD model,
executing the program simulator to determine the simulated current across the ESD model as through two or more predetermined circuit paths, and,
comparing the determined simulated current of the two or more circuit paths to the minimum current threshold, wherein if a current through the two or more circuit paths is above the minimum current threshold the current is unacceptably significant and the ESD circuit fails.
2. The method of claim 1 , wherein the ESD model further comprises an ESD circuit and one of a Human Body Model (HBM), a Machine Model (MM), or a Charged Device Model (CDM).
3. The method of claim 1 , wherein the ESD model is a Human Body Model (HBM) in communicative arrangement with an ESD circuit, and the semiconductor device is an integrated circuit (IC) design having IC characteristics.
4. The method of claim 3 , further comprising, returning a FAIL state where the determined simulated current through the ESD circuit is significantly less than the minimum current threshold or returning a PASS state where the determined simulated current is equal or very close to the minimum current threshold.
5. The method of claim 3 , further comprising, returning a PASS state where the determined simulated current through the ESD circuit is no more than approximately 10 micro amps less than the minimum current threshold.
6. The method of claim 3 , wherein the one or more predetermined circuit paths are as between the positive supply voltage (V CC ) of the ESD circuit and the ground point, a first input/output (I/O) point and a second I/O point of the IC, and one of the I/O points of the IC and the ground point.
7. The method of claim 3 , wherein characteristics of the HBM model include a resistor (R), an inductor (L), and a capacitor (C), configured in circuit communication where C is approximately in a range from 80 to 300 pF, R is approximately in a range of 800 to 3000 ohms, L is approximately in a range of 0.1 to 15 μH (micro Henrys).
8. The method of claim 7 , wherein C is at or about 100 to 250 pF, R is at or about 1000 to 2000 ohms and L is at or about 6 to 8 uH.
9. The method of claim 3 , wherein the program simulator is a modified SPICE program.
10. A method of estimating current leakage of an electrostatic discharge (ESD) circuit using a program simulator, comprising:
populating characteristics of a Human Body Model (HBM), a designed ESD device in communication with the HBM, and an associated semiconductor device under test (DUT), into the program simulator,
simulating current flow through at least two or more circuit paths as between a positive supply voltage (V CC ) of the HBM and the ground point, a first input/output (I/O) point and a second I/O point of the DUT, and one of the I/O points of the DUT and the ground point, and
determining a current leakage as an average difference between the simulated current flow through the at least two or more circuit paths and a minimum current threshold for the DUT; wherein if a current through the at least two or more circuit paths is above the minimum current threshold the current is unacceptably significant and the DUT fails.
11. The method of claim 10 , wherein when the determined current leakage is greater than zero, the ESD circuit fails.
12. The method of claim 10 , wherein when the determined current leakage is greater than 100uA, the ESD circuit fails.
13. The method of claim 12 , wherein characteristics of the HBM model include a resistor (R), an inductor (L), and a capacitor (C), configured in circuit communication where C is approximately in a range from 80 to 300 pF, R is approximately in a range of 800 to 3000 ohms, L is approximately in a range of 0.1 to 15 μH (micro Henrys).
14. The method of claim 13 , wherein C is at or about 100 to 250 pF, R is at or about 1000 to 2000 ohms and L is at or about 6 to 8 uH.
15. The method of claim 14 , wherein the program simulator is a modified SPICE program.
16. A computer program product for passing or failing an electrostatic discharge (ESD) circuit using a program simulator and an ESD model, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising: a first executable portion having instructions providing a capability of: populating characteristics of the ESD model and an associated semiconductor device into the program simulator,
determining a minimum current threshold for the ESD model,
executing the program simulator to determine the simulated current across the ESD model as through two or more predetermined circuit paths, and,
comparing the determined simulated current of the two or more circuit paths to the minimum current threshold, wherein if a current through the two or more circuit paths is above the minimum current threshold the current is unacceptably significant and the ESD circuit fails.
17. The product of claim 16 , wherein the ESD model further comprises an ESD circuit and one of a Human Body Model (HBM), a Machine Model (MM), or a Charged Device Model (CDM).
18. The product of claim 16 , wherein the ESD model is a Human Body Model (HBM) in communicative arrangement with an ESD circuit, and the semiconductor device is an integrated circuit (IC) design having IC characteristics.
19. The product of claim 18 , further comprising, returning a FAIL state where the determined simulated current is significantly less than the minimum current threshold or returning a PASS state where the determined simulated current is equal or very close to the minimum current threshold.
20. The product of claim 18 , further comprising, returning a PASS state where the determined simulated current is no more than approximately 100 micro amps less than the minimum current threshold.
21. The product of claim 18 , wherein the one or more predetermined circuit paths are as between the positive supply voltage (VCC) of the ESD model and the ground point, a first input/output (I/O) point and a second I/O point of the IC, and one of the I/O points of the IC and the ground point.
22. The product of claim 18 , wherein characteristics of the HBM model include a resistor (R), an inductor (L), and a capacitor (C), configured in circuit communication where C is approximately in a range from 80 to 300 pF, R is approximately in a range of 800 to 3000 ohms, L is approximately in a range of 0.1 to 15 μH (micro Henrys).
23. The product of claim 22 , wherein C is at or about 100 to 250 pF, R is at or about 1000 to 2000 ohms and L is at or about 6 to 8 uH.
24. The product of claim 18 , wherein the program simulator includes one or more scripts of a modified SPICE program.
25. The product of claim 18 , further comprising the step of identifying one or more weak links in the ESD circuit where the simulator returned a FAIL state.