IP Library Granted Patent US 7,781,806
Granted Patent B2
US 7,781,806 · App. 12/106,180 · Granted Aug 24, 2010

Optical erase memory structure

Assignee: Spansion LLC
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Quick Facts
Patent No.
US 7,781,806
App. No.
12/106,180
Granted
Aug 24, 2010
Kind
B2
Abstract

A method for providing an optical erase memory structure including: forming a metal-insulator-metal memory cell; positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and emitting a light emission from the light emitting diode for erasing the metal-insulator-metal memory cell.

Claims (35)

1. A method for providing an optical erase memory structure including:

forming a metal-insulator-metal memory cell having spacers that are transparent;

positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and

emitting a light emission from the light emitting diode through the spacers for erasing the metal-insulator-metal memory cell.

2. The method as claimed in claim 1 further comprising providing a light transmissive layer between the light emitting diode and the metal-insulator-metal memory cell.

3. The method as claimed in claim 1 further comprising depositing a reflective layer over the light emitting diode for redirecting the light emission.

4. The method as claimed in claim 1 further comprising forming a light channeling structure adjacent to the metal-insulator-metal memory cell for routing the light emission.

5. The method as claimed in claim 1 further comprising:

providing an optical erase memory structure application including mounting the optical erase memory structure therein; and

transferring a data pattern from the optical erase memory structure application to the optical erase memory structure.

6. A method for providing an optical erase memory structure including:

forming a metal-insulator-metal memory cell having spacers that are transparent including providing a charge trap layer;

positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and

emitting a light emission from the light emitting diode through the spacers for erasing the metal-insulator-metal memory cell including dissipating a charge in the charge trap layer.

7. The method as claimed in claim 6 further comprising providing a light transmissive layer between the light emitting diode and the metal-insulator-metal memory cell including providing a clear epoxy layer, a silicon dioxide layer, or a polyimide layer.

8. The method as claimed in claim 6 further comprising depositing a reflective layer over the light emitting diode for redirecting the light emission including forming a light channeling interface.

9. The method as claimed in claim 6 further comprising forming a light channeling structure adjacent to the metal-insulator-metal memory cell for routing the light emission including erasing a metal-insulator-metal memory cell array segment.

10. The method as claimed in claim 6 wherein positioning the light emitting diode adjacent to the metal-insulator-metal memory cell includes providing a complete substrate having the light emitting diode or mounting a second substrate, having the light emitting diode, over a first substrate.

11. An optical erase memory structure including:

a metal-insulator-metal memory cell with spacers that are transparent;

a light emitting diode adjacent to the metal-insulator-metal memory cell; and

a light emission from the light emitting diode through the spacers for erasing the metal-insulator-metal memory cell.

12. The apparatus as claimed in claim 11 further comprising a light transmissive layer between the light emitting diode and the metal-insulator-metal memory cell.

13. The apparatus as claimed in claim 11 further comprising a reflective layer over the light emitting diode for redirecting the light emission.

14. The apparatus as claimed in claim 11 further comprising a light channeling structure adjacent to the metal-insulator-metal memory cell for routing the light emission.

15. The apparatus as claimed in claim 11 further comprising:

an optical erase memory structure application includes a camera with the optical erase memory structure mounted therein; and

a data pattern transferred from the optical erase memory structure application to the optical erase memory structure includes picture data transferred from the camera.

16. The apparatus as claimed in claim 11 further comprising:

a charge trap layer in the metal-insulator-metal memory cell; and

a charge dissipated from the charge trap layer by the light emission.

17. The apparatus as claimed in claim 16 further comprising a light transmissive layer between the light emitting diode and the metal-insulator-metal memory cell includes a clear epoxy layer, a silicon dioxide layer, or a polyimide layer.

18. The apparatus as claimed in claim 16 further comprising a reflective layer over the light emitting diode for redirecting the light emission by a light channeling interface.

19. The apparatus as claimed in claim 16 further comprising a light channeling structure adjacent to the metal-insulator-metal memory cell for routing the light emission includes a metal-insulator-metal memory cell array segment erased.

20. The apparatus as claimed in claim 16 wherein a light emitting diode adjacent to the metal-insulator-metal memory cell includes a complete substrate having the light emitting diode or a second substrate, having the light emitting diode, mounted over a first substrate.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036042/0212 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2008
From: VANBUSKIRK, MICHAEL; MCCLAIN, MARK
To: SPANSION LLC
Reel/Frame 020827/0778 →
Continuity (1)
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