Semiconductor pixel arrays with reduced sensitivity to defects

1. A method for selecting a row of pixel structures or column of pixel structures, in an array of pixel structures logically organized in rows and columns, the method comprising:

selecting said row of pixel structures or said column of pixel structures, respectively, by applying a first signal to a first row select line associated with said row of pixel structures or by applying a first signal to a first column select line associated with said column of pixel structures; and

selecting said row of pixel structures or said column of pixel structures, respectively, by applying a second signal to a second row select line associated with said row of pixel structures or by applying a second signal to a second column select line associated with said column of pixel structures, wherein each of said row of pixel structures or said column of pixel structures has at least two row select lines or two column select lines, respectively, wherein each of said row select lines or said column select lines are connected to an ON/OFF switch, wherein each said ON/OFF switch is coupled in series between a photosensitive element and a pixel output line, wherein said second row select line or second column select line has a different timing than the first row select line or first column select line, respectively.

2. The method of claim 1 , wherein said pixel structures are active pixel structures.

3. The method of claim 1 , wherein said pixel structures are passive pixel structures.

4. The method of claim 1 , wherein said selection ON/OFF switches are MOSFETs.

5. The method of claim 1 , wherein one row or column of pixel structures shares a plurality of select lines, wherein each nth selection ON/OFF switch of pixel structures on one row or column being connected to an nth select line.

6. The method of claim 5 , wherein said plurality of select lines extends in parallel.