Nonvolatile memory device having a plurality of memory blocks
View Patent ↗A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC 1 and a first ground line VSS 1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC 2 and a second ground line VSS 2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.
1. A nonvolatile memory device provided with a plurality of memory blocks, the nonvolatile memory device comprising:
a rewrite control unit to which at least one of a first power source line and a first ground line are connected and which is operable to control a rewrite operation with respect to the memory blocks; and
a read control unit to which at least one of a second power source line and a second ground line are connected and which is operable to control a read operation with respect to the memory blocks, wherein the rewrite control unit and the read control unit are arranged so as to be spaced apart from one another.
2. The nonvolatile memory device in accordance with claim 1 , further comprising:
a first voltage generating unit that generates a bias voltage required at the time of the rewrite operation; and
a second voltage generating unit that generates a bias voltage required at the time of the read operation, wherein the first voltage generating unit is arranged close to the rewrite control unit, and wherein the second voltage generating unit is arranged close to the read control unit.
3. The nonvolatile memory device in accordance with claim 2 , wherein at least one of the first power source line and the first ground line are connected to the first voltage generating unit, and wherein at least one of the second power source line and the second ground line are connected to the second voltage generating unit.
4. The nonvolatile memory device in accordance with claim 2 , wherein the rewrite control unit is provided with a first switching unit that controls supply of a bias voltage generated by the first voltage generating unit to the memory blocks, and wherein the read control unit is provided with a second switching unit that controls supply of a bias voltage generated by the second voltage generating unit to the memory blocks.
5. The nonvolatile memory device in accordance with claim 4 , further comprising:
a command decoder; and
a block address decoder that identifies the memory blocks, wherein the first switching unit and the second switching unit are selected depending on decoding results of the command decoder and the block address decoder.
6. The nonvolatile memory device in accordance with claim 5 , wherein the first switching unit is selected with respect to the memory blocks to which the rewrite operation is requested, and wherein the second switching unit is selected with respect to a memory block other than the memory blocks to which the rewrite operation was requested.
7. The nonvolatile memory device in accordance with claim 3 , wherein the rewrite control unit is provided with a first switching unit that controls supply of a bias voltage generated by a first voltage generating unit to the memory blocks, and wherein the read control unit is provided with a second switching unit that controls supply of a bias voltage generated by the second voltage generating unit to the memory blocks.
8. The nonvolatile memory device in accordance with claim 4 , wherein the first switching unit is selected with respect to the memory blocks to which the rewrite operation is requested, and wherein the second switching unit is selected with respect to a memory block other than the memory blocks to which the rewrite operation was requested.
9. The nonvolatile memory device in accordance with claim 1 , wherein the rewrite control unit and the read control unit are arranged so as to face each other, with a memory cell block provided therebetween.
10. The nonvolatile memory device in accordance with claim 1 , wherein at least one of the first power source line and the first ground line and at least one of the second power source line and the second ground line are each connected to their dedicated terminals.
11. A nonvolatile memory device provided with a plurality of memory blocks, the nonvolatile memory device comprising:
a first voltage generating unit to which at least one of a first power source line and a first ground line are connected and which is operable to generate a bias voltage required at the time of a rewrite operation;
a sense amplifier to which at least one of a second power source line and a second ground line are connected and which is operable to sense memory cell data at the time of a read operation, wherein the first voltage generating unit and the sense amplifier are arranged so as to face each other with the memory blocks provided therebetween;
a rewrite memory block to which a bias voltage is applied from the first power generating unit; and
a read memory block to which the sense amplifier is connected.
12. The nonvolatile memory device in accordance with claim 11 , wherein a source terminal, a drain terminal, a gate terminal and a back gate terminal of a memory cell inside the rewrite memory block are connected to the first power source line, the first ground line or an output line of the first voltage generating unit, and wherein a source terminal, a drain terminal, a gate terminal and a back gate terminal of a memory cell inside the read memory block are connected to the second power source line, the second ground line or an internal power source line for read purposes generated from these lines.
13. The nonvolatile memory device in accordance with claim 12 , wherein the first voltage generating unit and the sense amplifier operate simultaneously.
14. The nonvolatile memory device in accordance with claim 11 , wherein the first voltage generating unit and the sense amplifier operate simultaneously.
15. The nonvolatile memory device in accordance with claim 11 , further comprising a first switching unit and a second switching unit, each being connected at one end thereof to a bit line connected to a drain terminal of a memory cell inside the memory blocks and arranged so as to face each other with the memory blocks provided therebetween, wherein the first switching unit is connected at the other end thereof to the first power source line, the first ground line or an output line of the first voltage generating unit, and wherein the second switching unit is connected at the other end thereof to the second power source line, the second ground line or an internal power source line for read purposes generated from these lines.
16. The nonvolatile memory device in accordance with claim 11 , further comprising a third switching unit and a fourth switching unit, each being connected at one end thereof to a source line or a bit line of a virtual ground-type connected to a source terminal of a memory cell inside the memory blocks, and arranged so as to oppose each other, with the memory blocks provided therebetween, wherein the third switching unit is connected at the other end thereof to the first power source line, the first ground line or an output line of the first voltage generating unit, and wherein the fourth switching unit is connected at the other end thereof to the second power source line, the second ground line or an internal power source line for read purposes generated from these lines.
17. The nonvolatile memory device in accordance with claim 11 , further comprising a fifth switching unit and a sixth switching unit, each being connected at one end thereof to a well line connected at a back gate terminal of a memory cell inside the memory blocks, and arranged so as to oppose each other with the memory blocks provided therebetween,
wherein the fifth switching unit is connected at the other end thereof to the first power source line, the first ground line or an output line of the first voltage generating unit, and wherein the sixth switching unit is connected at the other end thereof to the second power source line, the second ground line or an internal power source line for read purposes generated from these lines.
18. The nonvolatile memory device in accordance with claim 11 , further comprising a seventh switching unit and an eighth switching unit, each being connected at one end thereof to a word line connected to a gate terminal of a memory cell inside the memory blocks, and arranged so as to oppose each other with the memory blocks provided therebetween,
wherein the seventh switching unit is connected at the other end thereof to the first power source line, the first ground line or an output line of the first voltage generating unit, and wherein the eighth switching unit is connected at the other end thereof to the second power source line, the second ground line or an internal power source line for read purposes generated from these lines.