IP Library Granted Patent US 7,820,547
Granted Patent B2
US 7,820,547 · App. 12/179,400 · Granted Oct 26, 2010

Flash memory device with word lines of uniform width and method for manufacturing thereof

Assignee: Spansion LLC
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Quick Facts
Patent No.
US 7,820,547
App. No.
12/179,400
Granted
Oct 26, 2010
Kind
B2
Abstract

A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.

Claims (17)

1. A method for manufacturing a semiconductor device comprising:

forming a bit line in a semiconductor substrate;

forming a plurality of word lines, the plurality of word lines intersecting with the bit line at predetermined intervals on the semiconductor substrate;

eliminating a portion of the plurality of word lines comprising a region;

forming an interlayer insulating film on the semiconductor substrate; and

forming a metal plug, wherein the metal plug penetrates through the interlayer insulating film and is coupled to the bit line in the region where the portion of the plurality of word lines was eliminated.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising:

forming a conductive layer on the semiconductor substrate; and

forming a mask layer with a pattern at predetermined intervals on the conductive layer, wherein forming the plurality of word lines comprises forming the plurality of word lines by eliminating the conductive layer using the mask layer as a mask.

3. The method for manufacturing a semiconductor device according to claim 1 , further comprising:

forming a first conductive layer on the semiconductor substrate;

forming a second conductive layer on the first conductive layer; and

forming a mask layer, the mask layer comprising a pattern at predetermined intervals on the second conductive layer, wherein forming the plurality of word lines includes forming the plurality of word lines by eliminating the first conductive layer and the second conductive layer using the mask layer as a mask.

4. The method for manufacturing a semiconductor device according to claim 3 , further comprising eliminating an area of the first conductive layer where the bit line is to be formed, wherein forming the bit line includes forming the bit line by using the first conductive layer as a mask.

5. The method for manufacturing a semiconductor device according to claim 4 , further comprising forming a first insulating layer on the bit line between the first conductive layers, wherein forming the second conductive layer includes forming the second conductive layer on the first conductive layer and the first insulating layer.

6. The method for manufacturing a semiconductor device according to claim 1 , further comprising forming second insulating layers among the plurality of word lines, wherein eliminating the portion of the word lines is performed after forming the second insulating layers.

7. The method for manufacturing a semiconductor device according to claim 1 , further comprising forming a charge storage layer on the semiconductor substrate, wherein forming the word lines includes forming the word lines on the charge storage layer.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036042/0212 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2008
From: TAKAHATA, NAOFUMI; HIGASHI, MISAHIKO; UTSUNO, YUKIHIRO
To: SPANSION LLC
Reel/Frame 021469/0921 →
Priority Claims (1)
JP 2007-019752 · Jul 25, 2007 · national
Continuity (1)
Related Publication 20090184427A1 · Jul 23, 2009