Set and reset detection circuits for reversible resistance switching memory material
View Patent ↗Circuitry for performing a set or reset process for a reversible resistance-switching memory element in a memory device. A ramped voltage is applied to the memory cell and its state is constantly monitored so that the voltage can be discharged as soon as the set or reset process is completed, avoiding possible disturbs to the memory cell. One set circuit ramps the voltage using a current source, while detecting a current peak using an op-amp loop. One reset circuit ramps the voltage using an op-amp loop, while detecting a current peak by continuing to draw current at the peak current to maintain the output signal stable. Another set circuit ramps the voltage using an op-amp loop and a source-follower configuration. Another reset circuit ramps the voltage using an op-amp loop and a source-follower configuration with level shifting to reduce power consumption. Faster detection and shutoff, and stable operation, are achieved.
1. Apparatus for detecting a set process for a reversible resistance-switching element in a memory device, comprising:
a bit line which is coupled to the reversible resistance-switching element;
a current supply, the bit line is connected as a current mirror of the current supply, the current supply causes a voltage of the bit line to ramp up until the voltage of the bit line is sufficient to switch a resistance of the reversible resistance-switching element to a lower level; and
a peak detector which is coupled to the bit line, the peak detector detects when the resistance of the reversible resistance-switching element switches.
2. The apparatus of claim 1 , further comprising:
a pre-charge circuit which pre-charges the bit line before the voltage of the bit line is ramped up.
3. The apparatus of claim 2 , wherein:
the peak detector comprises an operational amplifier, a first input terminal of the operational amplifier is coupled to the bit line, and an output signal of the operational amplifier is inverted when the resistance of the reversible resistance-switching element is switched; and
the pre-charge circuit pre-charges a second input terminal of the operational amplifier while pre-charging the bit line.
4. The apparatus of claim 1 , further comprising:
a discharge transistor which is responsive to the peak detector, the discharge transistor discharges the bit line when an output signal of the peak detector is inverted.
5. Apparatus for detecting a reset process for a reversible resistance-switching element in a memory device, comprising:
an operational amplifier, a ramped up voltage is input to a first input terminal of the operational amplifier;
a bit line which is coupled to the reversible resistance-switching element;
the operational amplifier generates a voltage in the bit line which increases in correspondence with the ramped up voltage until the voltage in the bit line reaches a level which is sufficient to switch a resistance of the reversible resistance-switching element to a higher level;
a sense line, the operational amplifier generates a current in the sense line which increases in correspondence with the ramped up voltage until the resistance of the reversible resistance-switching element switches to a higher level;
a peak detector coupled to the sense line, the peak detector detects when the resistance of the reversible resistance-switching element switches, and includes circuitry which draws current from the sense line before and after the reversible resistance-switching element switches.
6. The apparatus of claim 5 , wherein:
the circuitry draws current from the sense line at a peak level after the peak level is reached.
7. The apparatus of claim 5 , wherein:
the circuitry includes a transistor which is coupled between the sense line and ground, and a component which is coupled to the sense line and holds a charge at a gate of the transistor to draw current from the sense line before and after the reversible resistance-switching element switches.
8. The apparatus of claim 5 , wherein:
a voltage on the sense line is substantially constant while the current in the sense line increases until a peak level is reached, after which the voltage on the sense line drops.
9. The apparatus of claim 5 , further comprising:
a switch in the sense line, the switch is made conductive after a predetermined delay after a time when the ramped up voltage is first input to the first input terminal of the operational amplifier.
10. Apparatus for detecting a set process for a reversible resistance-switching element in a memory device, comprising:
an operational amplifier, a ramped up voltage is input to a first input terminal of the operational amplifier;
a first transistor having a gate which is coupled to the operational amplifier, the operational amplifier provides a voltage at the gate, a voltage at a source of the first transistor follows the voltage at the gate;
a bit line which is coupled to the reversible resistance-switching element and to the source of the first transistor; and
a comparator having a first input terminal coupled to a drain of the first transistor and a second input terminal which receives a fixed reference voltage.
11. The apparatus of claim 10 , wherein:
when the ramped up voltage is input to the first input terminal of the operational amplifier, the voltage at the bit line is ramped up until it reaches a level which is sufficient to switch a resistance of the reversible resistance-switching element to a lower level, at which time a voltage at the drain of the first transistor drops below a level of the fixed reference voltage, thereby inverting an output signal of the comparator.
12. The apparatus of claim 10 , further comprising:
a reference current source coupled to the source of the first transistor.
13. The apparatus of claim 10 , further comprising:
a second transistor having a gate which is coupled to the operational amplifier; and
a current source coupled to a source of the second transistor.
14. Apparatus for detecting a reset process for a reversible resistance-switching element in a memory device, comprising:
an operational amplifier, a ramped up voltage is input to a first input terminal of the operational amplifier;
a first transistor having a gate which is coupled to the operational amplifier, the operational amplifier provides a voltage at the gate, a voltage at a source of the first transistor follows the voltage at the gate;
a bit line which is coupled to the reversible resistance-switching element and to the source of the first transistor;
a sense line which is connected as a mirror of the bit line; and
a peak detector coupled to the sense line to detect when a resistance of the reversible resistance-switching element switches to a higher level.
15. The apparatus of claim 14 , wherein:
the sense line is connected as the mirror of the bit line via a pair of mirror pMOS transistors, gates of the mirror pMOS transistors are coupled to a drain of the first transistor via a charge storage component.
16. The apparatus of claim 15 , further comprising:
at least a first switch which is controlled to charge the charge storage component before the ramped up voltage is input to the first input terminal of the operational amplifier.
17. The apparatus of claim 14 , wherein:
the sense line is connected as the mirror of the bit line via a pair of pMOS mirror transistors, each pMOS mirror transistor is in a conductive state with a negative gate-to-source voltage.
18. The apparatus of claim 14 , wherein:
the peak detector comprises an inverter coupled to the sense line, an output of the inverter is inverted when the resistance of the reversible resistance-switching element switches to the higher level.
19. The apparatus of claim 14 , further comprising:
circuitry coupled to the sense line which draws current from the sense line at a peak level after the resistance of the reversible resistance-switching element switches to the higher level.
20. The apparatus of claim 14 , wherein:
the operational amplifier generates a ramped up output voltage, a voltage in the bit line is ramped up in correspondence with the ramped up output voltage until the voltage in the bit line reaches a level which is sufficient to switch the resistance of the reversible resistance-switching element to the higher level, a voltage in the sense line is ramped up in correspondence with the ramped up output voltage, after which the voltage in the sense line drops.