Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element, and methods of forming the same
View Patent ↗In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and etching the CNT seeding layer, and selectively fabricating CNT material on the CNT seeding layer. Numerous other aspects are provided.
1. A method of fabricating a memory cell, the method comprising:
fabricating a steering element above a substrate; and
fabricating a reversible-resistance switching element coupled to the steering element by:
fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate;
patterning and etching the CNT seeding layer; and
selectively fabricating CNT material on the CNT seeding layer.
2. The method of claim 1 , wherein patterning and etching the CNT seeding layer includes patterning and etching the steering element.
3. The method of claim 1 , wherein selectively fabricating CNT material on the CNT seeding layer includes depositing CNT material on the CNT seeding layer using chemical vapor deposition.
4. The method of claim 1 , further comprising creating defects in the CNT material to tune switching characteristics of the CNT material.
5. The method of claim 1 , wherein the reversible-resistance switching element is fabricated above the steering element.
6. The method of claim 1 , wherein fabricating the steering element comprises fabricating a p-n or p-i-n diode.
7. The method of claim 1 , wherein fabricating the steering element comprises fabricating a polycrystalline diode.
8. The method of claim 1 , wherein fabricating the steering element comprises fabricating a vertical polycrystalline diode.
9. The method of claim 1 , wherein fabricating the steering element comprises fabricating a vertical polycrystalline diode having polycrystalline material that is in a low-resistivity state.
10. The method of claim 1 , wherein fabricating the steering element comprises fabricating a thin film transistor.
11. The method of claim 1 , wherein fabricating the steering element comprises fabricating a thin film, metal oxide semiconductor field effect transistor.
12. The method of claim 1 , wherein selectively fabricating the CNT material includes fabricating CNT material having CNTs that are substantially vertically aligned to reduce lateral conduction in the CNT material.
13. A method of fabricating a memory cell, the method comprising:
fabricating a first conductor above a substrate;
fabricating a reversible-resistance switching element above the first conductor by:
fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the first conductor;
patterning and etching the CNT seeding layer; and
selectively fabricating CNT material on the CNT seeding layer;
fabricating a diode above the first conductor; and
fabricating a second conductor above the diode and the reversible resistance-switching element.
14. The method of claim 13 , wherein patterning and etching the CNT seeding layer includes patterning and etching the diode.
15. The method of claim 13 , wherein the reversible-resistance switching element is fabricated above the diode.
16. The method of claim 13 , wherein fabricating the diode comprises fabricating a vertical polycrystalline diode.
17. The method of claim 13 , further comprising fabricating a silicide, silicide-germanide or germanide region in contact with polycrystalline material of the vertical polycrystalline diode so that the polycrystalline material is in a low-resistivity state.
18. The method of claim 13 , wherein selectively fabricating the CNT material includes fabricating CNT material having CNTs that are substantially vertically aligned so as to reduce lateral conduction in the CNT material.
19. A method of fabricating a memory cell, the method comprising:
fabricating a thin film transistor having a source region and a drain region;
fabricating a first conductor coupled to the source region or the drain region of the transistor;
fabricating a reversible-resistance switching element coupled to the first conductor by:
fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the first conductor;
patterning and etching the CNT seeding layer; and
selectively fabricating CNT material on the CNT seeding layer;
fabricating a diode above the first conductor; and
fabricating a second conductor above the reversible resistance-switching element.
20. The method of claim 19 , wherein selectively fabricating the CNT material includes fabricating CNT material having CNTs that are substantially vertically aligned so as to reduce lateral conduction in the CNT material.