IP Library Granted Patent US 8,321,623
Granted Patent B2
US 8,321,623 · App. 12/434,650 · Granted Nov 27, 2012

Ad hoc flash memory reference cells

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Quick Facts
Patent No.
US 8,321,623
App. No.
12/434,650
Granted
Nov 27, 2012
Kind
B2
Abstract

In a nonvolatile memory, that includes cells organized in a plurality of bit lines and a plurality of word lines, user data are stored in respective portions of each of two of the word lines. Control information is stored in a cell that is common to one of the bit lines and one of the two word lines. A cell that is common to the bit line and the other word line is used as a reference cell. A flash memory, that includes a plurality of primary cells and a plurality of spare cells, is interrogated to determine which spare cells have been used to replace respective primary cells. At least some of the other spare cells are used as reference cells.

Claims (36)

1. A method of managing a nonvolatile memory that includes a plurality of cells organized in a plurality of bit lines and a plurality of word lines, the method comprising:

(a) storing user data in respective portions of the cells of each of two of the word lines; and

(b) in one of the bit lines that is shared by the two word lines:

(i) storing control information in a cell corresponding to the one bit line and a first of the two word lines, and

(ii) using a cell corresponding to the one bit line and a second of the two word lines as a reference cell.

2. The method of claim 1 , wherein the user data are stored only in cells other than the cells of the one bit line that includes the reference cell.

3. The method of claim 1 , wherein the first and second word lines are in a common block of the nonvolatile memory.

4. The method of claim 3 , wherein said control information is block-level management information for managing the common block.

5. The method of claim 1 , wherein the first and second word lines are in separate respective blocks of the nonvolatile memory.

6. The method of claim 5 , wherein the control information is error correction code information.

7. A controller, for a flash memory that includes a plurality of cells organized in a plurality of bit lines and a plurality of word lines, the controller being operative:

(a) to store user data in respective portions of the cells of each of two of the word lines; and

(b) in one of the bit lines that is shared by the two word lines:

(i) to store control information in a cell corresponding to the one bit line and a first of the two word lines, and

(ii) to use a cell corresponding to the one bit line and a second of two word lines as a reference cell.

8. A flash memory device comprising:

(a) a flash memory including a plurality of cells organized in a plurality of bit lines and a plurality of word lines; and

(b) a controller operative:

(i) to store user data in respective portions of the cells of each of two of the word lines, and

(ii) in one of the bit lines that is shared by the two word lines:

(A) to store control information in a cell corresponding to the one bit line and a first of the two word lines, and

(B) to use a cell corresponding to the one bit line and a second of two word lines as a reference cell.

9. A system comprising:

(a) a flash memory including a plurality of cells organized in a plurality of bit lines and a plurality of word lines;

(b) a host, of the flash memory, including:

(i) a memory for storing code for managing the flash memory by steps including:

(A) storing user data in respective portions of the cells of each of two of the word lines, and

(B) in one of the bit lines that is shared by the two word lines:

(I) storing control information in a cell corresponding to the one bit line and a first of the two word lines, and

(II) using a cell corresponding to the one bit line and a second of the two word lines as a reference cell, and

(ii) a processor for executing the code.

10. A computer-readable storage medium having embodied thereon computer-readable code for managing a flash memory that includes a plurality of cells organized in a plurality of bit lines and a plurality of word lines, the computer-readable code comprising:

(a) program code for storing user data in respective portions of the cells of each of two of the word lines; and

(b) program code for, in one of the bit lines that is shared by the two word lines:

(i) storing control information in a cell corresponding to the one bit line and a first of the two word lines, and

(ii) using a cell corresponding to the one bit line and a second of the two word lines as a reference cell.

Assignments (6)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2014
From: SANDISK IL LTD.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 033070/0041 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2009
From: MURIN, MARK; SHARON, ERAN
To: SANDISK IL LTD.
Reel/Frame 022628/0886 →