Pixel structure having shielded storage node

1. A pixel comprising:

a sample transistor coupled to a light detecting stage, the sample transistor comprising an inner junction region coupled to a storage node, and a gate disposed around at least three sides of the inner junction region that operates as a charge barrier to protect the inner junction region from charges collected in response to light and to reduce a parasitic light sensitivity (PLS) of the pixel; and

a memory capacitor coupled to the storage node.

2. The pixel of claim 1 , wherein the sample transistor further comprises an outer junction region disposed around the inner junction region.

3. The pixel of claim 2 , wherein the charge barrier protects the inner junction region from charges generated in the outer junction region.

4. The pixel of claim of claim 3 , wherein the outer junction region collects light generated close to the inner junction region.

5. The pixel of claim 1 , further comprising a light shield that shields the inner junction region from light received by the pixel in operation.

6. The pixel of claim 5 , wherein the light shield substantially does not shield the outer junction region from light received by the pixel in operation.

7. The pixel of claim 1 , wherein the charge barrier forms an open ring around the inner junction region.

8. The pixel of claim 1 , wherein the charge barrier forms a closed ring around the inner junction region.

9. The pixel of claim 1 , wherein the pixel is a six transistor (6T) pixel.

10. The pixel of claim 1 , further comprising one or more additional sample transistors having a gate disposed around an inner junction region that operates as a charge barrier.

11. A synchronous shutter image sensor comprising a plurality of the pixels of claim 1 .

12. A method comprising generating an active-pixel layout including a sample transistor having an inner junction region, an outer junction region disposed around the inner junction region, and a gate charge barrier disposed around at least three sides of the inner junction region that operates as a charge barrier to protect the inner junction region from charges generated in the outer junction region and to reduce a parasitic light sensitivity (PLS).

13. The method of claim 12 , wherein generating the active-pixel layout further comprises generating the pixel layout to have a storage node coupled to the inner junction region.

14. The method of claim 12 , wherein generating the active-pixel layout comprises laying out the gate to form an open ring around the inner junction region.

15. The method of claim 12 , wherein generating the active-pixel layout comprises laying out the gate to form a closed ring around the inner junction region.

16. An apparatus comprising an active-pixel sensor including a sample transistor having an inner junction region, an outer junction region disposed in a closed ring around the inner junction region, and means for reducing a parasitic light sensitivity (PLS) of the pixel by protecting the inner junction region from charges generated by light in the outer junction region.

17. The apparatus of claim 16 , wherein the means for reducing the PLS comprises a charge barrier disposed around at least three sides of the storage node.

18. The apparatus of claim 17 , wherein the charge barrier operates as a gate of the sample transistor in operation of the active-pixel sensor.

19. The pixel of claim 17 , wherein the charge barrier forms a closed ring around the inner junction region.