Polarity dependent switch for resistive sense memory
View Patent ↗Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.
1. A method of forming a memory unit comprising;
implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor; and
electrically connecting a resistive sense memory cell to the bit contact, the resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.
2. A method according to claim 1 , wherein the implanting step comprises halo implanting a dopant material in the source contact and not in the bit contact.
3. A method according to claim 1 , wherein during the implantation step the bit contact is masked with a photoresist layer.
4. A method according to claim 1 , wherein the implanting dopant material more heavily in a source contact than a bit contact comprises implanting dopant material at an angle of less than 90 degrees relative to a major surface of the substrate.
5. A method according to claim 1 , wherein the implanting step comprises implanting a first amount of dopant material in the source contact and implanting a second amount of dopant material in the bit contact and the first amount is greater than the second amount.
6. A method according to claim 1 , wherein the implanting step comprises implanting boron in the source contact and not in the bit contact.
7. A method according to claim 1 , wherein the implanting step comprises forming a lightly doped drain region in the bit contact.
8. A method according to claim 2 , wherein the implanting step comprises forming a lightly doped drain region in the bit contact.
9. A method according to claim 8 , wherein the implanting step comprises forming a lightly doped drain region in the bit contact and the bit contact is not halo implanted.
10. A method according to claim 1 , wherein the electrically connecting step comprises electrically connecting a spin-torque transfer memory cell to the bit contact.
11. A method according to claim 1 , further comprising applying a write current in an easy direction through the source contact before the bit contact.
12. A method according to claim 11 , further comprising applying a write current in a hard direction through the bit contact before the source contact.
13. A method according to claim 3 , wherein during the implantation step the bit contact is masked with a photoresist layer while halo implanting a dopant material in the source contact and not in the bit contact.
14. A method of forming a memory unit comprising;
asymmetrically implanting more dopant material in a source contact than a bit contact of a semiconductor transistor; and
electrically connecting a resistive sense memory cell to the bit contact, the resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.
15. A method according to claim 14 , wherein the asymmetrically implanting step comprises halo implanting a dopant material in the source contact and not in the bit contact.
16. A method according to claim 14 , wherein during the asymmetrically implanting step the bit contact is masked with a photoresist layer.
17. A method according to claim 14 , wherein the asymmetrically implanting step comprises implanting dopant material at an angle of less than 90 degrees relative to a major surface of the substrate.
18. A method according to claim 14 , wherein the asymmetrically implanting step comprises forming a lightly doped drain region in the bit contact.
19. A method according to claim 14 , wherein the electrically connecting step comprises electrically connecting a spin-torque transfer memory cell to the bit contact.
20. A method of forming a memory unit comprising;
implanting a halo dopant material more heavily in a source contact than a bit contact of a semiconductor transistor and forming a lightly doped drain region in the bit contact; and
electrically connecting a resistive sense memory cell to the bit contact, the resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.