Method for performing a return operation in parallel with setting status flags based on a return value register test
View Patent ↗Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting status flags. Testing the content of the return value register and setting the status flags are performed in response to a single instruction.
1. A method comprising:
receiving a single instruction that includes a return operation;
dividing the single instruction into a first micro-operation and a second micro-operation in an instruction decode stage, wherein the first micro-operation is configured for performing the return operation and the second micro-operation is configured for performing a test operation;
reading, using the first micro-operation, information associated with a return address from a register file in the instruction decode stage;
providing, using the first micro-operation, the information associated with the return address to an arithmetic logic unit in an execution stage;
reading, using the second micro-operation in the instruction decode stage in parallel with the first micro-operation in the execution stage, a content of a return value register;
responsive to the reading using the second micro-operation in the instruction decode stage, testing the content of the return value register using the second micro-operation in the execution stage;
setting, using the second micro-operation in the execution stage, status flags that includes writing a value into a flag register based on testing the content of the return value register; and
providing, while the first micro-operation is in a memory stage in parallel with the second micro-operation in the execution stage, the information associated with the return address to a pipeline register connected to a multiplexer included in a writeback stage, the multiplexer configured for sending the information associated with the return address to a program counter via an output of the multiplexer.
2. The method of claim 1 , wherein the status flags are set according to a comparison of the content of the return value register with zero.
3. The method of claim 1 , wherein the single instruction is kept in the instruction decode stage for an additional cycle after the single instruction is fetched.
4. The method of claim 1 , wherein the status flags are set before the information associated with the return address is written to the program counter, the information including a content of a return address register.
5. The method of claim 1 , wherein testing the content of the return value register is performed without receiving a test instruction.
6. The method of claim 1 , further comprising:
loading consecutive words pointed to by a register pointer into a register specified by the single instruction, wherein the content of the return value register is tested and the status flags are updated if a program counter is loaded.
7. A processing unit comprising:
a program counter, wherein the processing unit is configured to execute a single instruction that includes a return operation and is divided into a first micro-operation and a second micro-operation in an instruction decode stage, wherein:
the first micro-operation is configured to return information associated with a return address and provide, based on execution of the first micro-operation in a memory stage, the information to a multiplexer included in a writeback stage; and
the second micro-operation is configured to test, in an execution stage in parallel with the first micro-operation in the memory stage, a content of a return value register and set status flags including writing a value into a flag register based on testing the content of the return value register; and
the multiplexer configured to send the information associated with the return address to a program counter via an output of the multiplexer.
8. The processing unit of claim 7 , wherein the first micro-operation is configured to route a first control signal associated with the return address past an arithmetic logic unit of the processing unit before setting of the status flags.
9. The processing unit of claim 8 , further comprising a second multiplexer, the second multiplexer including a first input coupled to the output of the multiplexer included in the writeback stage to receive the information associated with the return address, a node to receive a second control signal, and an output to enable writing the information associated with the return address to the program counter when the second control signal has a first value.
10. The processing unit of claim 9 , wherein the second multiplexer further includes a second input to receive a sequential program address, and wherein the second multiplexer is further configured to enable updating of the program counter with the sequential program address when the second control signal has a second value.
11. The processing unit of claim 8 , wherein the information associated with the return address includes a return address read from data memory, and wherein the processing unit further comprises a second multiplexer, the second multiplexer including a first input coupled to the output of the multiplexer included in the writeback stage to receive the return address read from the data memory, a node to receive a second control signal, and an output to enable writing the return address read from the data memory to the program counter when the second control signal has a first value.
12. The processing unit of claim 11 , wherein the second multiplexer further includes a second input to receive a sequential program address, and wherein the second multiplexer is further configured to enable updating of the program counter with the sequential program address when the second control signal has a second value.
13. The processing unit of claim 7 , wherein the second micro-operation is configured to test the content of the return value register in order to determine whether return conditions are satisfied.
14. A non-transitory processor-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform operations including:
receiving a single instruction that includes a return operation;
dividing the single instruction into a first micro-operation and a second micro-operation in an instruction decode stage, wherein the first micro-operation is configured for performing the return operation and the second micro-operation is configured for performing a test operation;
reading, using the first micro-operation, information associated with a return address from a register file in the instruction decode stage;
providing, using the first micro-operation, the information associated with the return address to an arithmetic logic unit in an execution stage;
reading, using the second micro-operation in the instruction decode stage in parallel with the first micro-operation in the execution stage, a content of a return value register;
responsive to the reading using the second micro-operation in the instruction decode stage, testing the content of the return value register using the second micro-operation in the execution stage;
setting, using the second micro-operation in the execution stage, status flags that includes writing a value into a flag register based on testing the content of the return value register; and
providing, while the first micro-operation is in a memory stage in parallel with the second micro-operation in the execution stage, the information associated with the return address to a pipeline register connected to a multiplexer included in a writeback stage, the multiplexer configured for sending the information associated with the return address to a program counter via an output of the multiplexer.
15. The non-transitory processor-readable storage medium of claim 14 , wherein the instructions further cause the processor to perform operations including:
writing a content of a return address register to the program counter in response to a first value of a first control signal; and
writing a return address read from data memory to the program counter in response to a second value of the first control signal.
16. The non-transitory processor-readable storage medium of claim 15 , wherein the instructions further cause the processor to perform operations including updating the program counter with a sequential program address in response to a second control signal, and wherein writing the content of the return address register to the program counter and writing the return address read from data memory are performed when the second control signal has a first value, and updating the program counter with the sequential program address is performed when the second control signal has a second value, regardless of a value of the first control signal.