IP Library Granted Patent US 8,274,999
Granted Patent B2
US 8,274,999 · App. 12/830,268 · Granted Sep 25, 2012

Method and apparatus for analyzing and qualifying packet networks

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Quick Facts
Patent No.
US 8,274,999
App. No.
12/830,268
Granted
Sep 25, 2012
Kind
B2
Abstract

Packet network performance is assessed using transit delay metrics and compliance masks generated at various evaluation nodes of the network. The evaluation nodes may employ network probes that make precise measurements of transit delays and thereby of transit delay variations. Based on the assessments, a master may be added to the network or relocated within the network, rate of timing packets generated by the master may be adjusted up or down, or oscillators used at the slaves may be upgraded.

Claims (38)

1. A method of validating a network having one or more master clocks for packet-based timing transfer, comprising the steps of:

transmitting timing packets throughout the network;

receiving the timing packets at an evaluation node of the network;

computing a transit delay characteristic of the network based on timing information contained in the received timing packets;

generating a compliance mask for validating the network; and

comparing the transit delay characteristic against the compliance mask and validating the network based on the comparison.

2. The method according to claim 1 , further comprising the steps of:

receiving the timing packets at a second evaluation node of the network;

computing a second transit delay characteristic of the network based on timing information contained in the received timing packets;

generating a second compliance mask for validating the network; and

comparing the second transit delay characteristic against the second compliance mask and validating the network based on the comparison.

3. The method according to claim 2 , wherein the network is validated as suitable if the computed transit delay characteristics do not exceed their respective compliance masks.

4. The method according to claim 1 , further comprising:

if the transit delay characteristic exceeds the compliance mask, inserting a new master clock in the network.

5. The method according to claim 1 , further comprising:

if the transit delay characteristic exceeds the compliance mask, relocating a master clock in the network.

6. The method according to claim 1 , wherein the transit delay characteristic includes TDEV and MTIE and the compliance mask is one of a TDEV-based mask and a MTIE-based mask.

7. The method according to claim 1 , wherein the transit delay characteristic is computed for a time interval of at least T seconds, and the comparison with the compliance mask for network validation is performed only at time T.

8. The method according to claim 7 , further comprising:

computing T based on a property of an oscillator used at the evaluation node.

9. The method according to claim 8 ,

if the transit delay characteristic exceeds the compliance mask at time T, replacing the oscillator used at the evaluation node so that T is increased.

10. A method of deploying a network having one or more masters and a plurality of slaves that are synchronized to the masters, comprising the steps of:

at each of the slaves, computing a transit delay metric and a compliance mask based on timing packets transmitted by the masters, and a pivot point based on a property of an oscillator used at the slave; and

upgrading the network upon determining that, at one of the slaves, the transit delay metric exceeds the compliance mask at the pivot point of said one of the slaves.

11. The method according to claim 10 , wherein upgrading the network includes adding a master to the network.

12. The method according to claim 10 , wherein upgrading the network includes relocating a master within the network.

13. The method according to claim 10 , wherein upgrading the network includes upgrading an oscillator used at said one of the slaves.

14. The method according to claim 10 , wherein the transit delay characteristic includes TDEV and MTIE and the compliance mask is one of a TDEV-based mask and a MTIE-based mask.

15. A packet network comprising:

one or more master clocks;

one or more slave clocks;

a plurality of network elements between the master clocks and the slave clocks; and

a network management system coupled to each of the master clocks, the slave clocks, and the network elements, the network management system being configured to generate transit delay metrics and compliance masks at the slave clocks for active monitoring of the packet network performance.

16. The packet network according to claim 15 , further comprising a packet probe device co-located in the packet network with one of the slave clocks.

17. The packet network according to claim 16 , wherein the packet probe device is coupled to an accurate timing reference.

18. The packet network according to claim 17 , wherein the network management system computes the transit delay metric for the slave clock co-located with the packet probe device for a time interval of at least T seconds, and evaluates the transit delay metric at time T against a value of the compliance mask of the slave clock at time T, wherein T is determined from a property of an oscillator used at the slave clock.

19. The packet network according to claim 15 , wherein the network management system determines a rate at which timing packets are generated by the master clocks based on the transit delay metrics and the compliance masks.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
SECURITY AGREEMENT Recorded Apr 22, 2015
From: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP; MICROSEMI SEMICONDUCTOR (U.S.) INC.; MICROSEMI SOC CORP.; MICROSEMI FREQUENCY AND TIME CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 035477/0057 →
CHANGE OF NAME Recorded Feb 13, 2014
From: SYMMETRICOM, INC.
To: MICROSEMI FREQUENCY AND TIME CORPORATION
Reel/Frame 032264/0195 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2010
From: SHENOI, KISHAN; ZAMPETTI, GEORGE P.; COSART, LEE
To: SYMMETRICOM, INC.
Reel/Frame 024638/0853 →