IP Library Granted Patent US 8,149,012
Granted Patent B2
US 8,149,012 · App. 12/890,436 · Granted Apr 3, 2012

Deliberate destruction of integrated circuits

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Quick Facts
Patent No.
US 8,149,012
App. No.
12/890,436
Granted
Apr 3, 2012
Kind
B2
Abstract

A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.

Claims (25)

1. A method for intentionally permanently disabling a target device, the method comprising rapidly discharging at least one capacitor to a selected target signal path of the target device, wherein the discharging comprises a shaped high energy impulse to destroy one or more electronic devices of the target device.

2. The method of claim 1 , further comprising preconditioning the selected target signal path of the target device by applying a preconditioning current prior to the discharging of the at least one capacitor.

3. The method of claim 1 , further comprising disconnecting a power supply of the target device prior to the discharging of the at least one capacitor.

4. The method of claim 1 , further comprising disconnecting a power supply of the target device and connecting the power supply to ground prior to the discharging of the at least one capacitor.

5. The method of claim 1 , wherein the target device comprises an integrated circuit having the one or more electronic devices.

6. The method of claim 1 , further comprising detecting if the at least one capacitor is charged.

7. The method of claim 1 , wherein the shaped high energy impulse has a current in the range of 10 Amps to 200 Amps.

8. The method of claim 1 , wherein the at least one capacitor is a low Equivalent Series Resistance capacitor.

9. A disabling device configured to intentionally permanently disable an integrated circuit device, the disabling device comprising:

a central energy storage unit electrically connected to a power supply;

a target device electrically connected to the central energy storage unit, wherein the target device comprises the integrated circuit device and at least one target signal path, and

a controller configured to destroy the integrated circuit device by charging the central energy storage unit, and rapidly discharging the central energy storage unit to the at least one target signal path;

wherein the discharging applies a shaped high energy impulse to destroy the integrated circuit device of the target device.

10. The disabling device of claim 9 , wherein the rise time of the discharging is characterized by a dV/dt of greater than 1.5 volts/nanosecond.

11. The disabling device of claim 9 , wherein the disabling device is 260 mm 3 or less in size.

12. A method of power management for circuit destruction, the method comprising:

preconditioning a target pathway to at least one electronic device of a target device; and

discharging, from a disabling device, a shaped energy impulse through the target device to facilitate destruction of the at least one electronic device.

13. The method of claim 12 , further comprising disconnecting a target device power supply from the target device.

14. The method of claim 13 , further comprising connecting the target device power supply to ground.

15. The method of claim 12 , further comprising testing the target pathway to the at least one electronic device prior to the discharging the shaped energy impulse.

16. The method of claim 12 , further comprising testing the target pathway to the at least one electronic device after the discharging the shaped energy impulse.

17. The method of claim 12 , wherein the shaped energy impulse is charged by a power source having less wattage than the target device power supply.

18. The method of claim 12 , wherein the power level required to generate the shaped energy impulse is equal to or less than the power level required for normal operation of the target device.

19. The method of claim 12 , wherein power is only provided to the at least one electronic device.

Assignments (9)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2016
From: SMART STORAGE SYSTEMS, INC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038290/0033 →
CHANGE OF NAME Recorded May 29, 2013
From: SMART STORAGE SYSTEMS (AZ), INC.
To: SMART STORAGE SYSTEMS, INC.
Reel/Frame 030508/0855 →
CHANGE OF NAME Recorded May 29, 2013
From: SMART MODULAR TECHNOLOGIES (AZ), INC.
To: SMART STORAGE SYSTEMS (AZ), INC.
Reel/Frame 030508/0843 →
CHANGE OF NAME Recorded Jul 18, 2011
From: ADTRON CORPORATION
To: SMART MODULAR TECHNOLOGIES (AZ), INC.
Reel/Frame 026603/0986 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2010
From: LAZARAVICH, ROBERT; LITTLEBURY, HUGH; ELLIS, ROBERT WILLIAM
To: ADTRON CORPORATION
Reel/Frame 025463/0139 →