Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip

1. A ferro-electric random access memory (FRAM) chip, comprising:

a substrate;

a first dielectric layer over the substrate;

a gate over the first dielectric layer;

a first aluminum oxide layer over the first dielectric layer and the gate;

a second dielectric layer over the first aluminum oxide layer;

a trench through the second dielectric layer and the first aluminum oxide layer to the gate;

a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate, wherein the hydrogen barrier liner includes at least one of: an iridium oxide and iridium layer, a first titanium layer over the iridium oxide and iridium layer, and a second aluminum oxide layer over the first titanium layer; or a platinum layer, a first titanium layer over the platinum layer, and a second aluminum oxide layer over the first titanium layer; and

a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.

2. The chip of claim 1 , further comprising:

a source and a drain within the substrate;

a first metal layer partially over the second dielectric layer, over the silicon dioxide plug, and contacting a portion of the hydrogen barrier liner; and

at least one tungsten contact connecting the first metal layer and at least one of the source and the drain.

3. The chip of claim 2 , wherein the first metal layer includes a metal wire, wherein the metal wire includes copper or aluminum.

4. The chip of claim 2 , wherein the first metal layer includes a liner and a metal wire over the liner, the liner including a second titanium layer, a tantalum nitrite layer over the second titanium layer, and a tantalum layer over the tantalum nitrite layer.

5. The chip of claim 1 , further comprising:

a layer of second metal over the silicon dioxide plug, the layer of second metal including a titanium nitride layer and a third second titanium layer over the titanium nitride layer.

6. A ferro-electric random access memory (FRAM) chip, comprising:

a substrate;

a first dielectric layer over the substrate;

a gate over the first dielectric layer;

a first aluminum oxide layer over the first dielectric layer and the gate;

a second dielectric layer over the first aluminum oxide layer;

a trench through the second dielectric layer and the first aluminum oxide layer to the gate;

a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate;

a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench;

a source and a drain within the substrate;

a first metal layer partially over the second dielectric layer, over the silicon dioxide plug, and contacting a portion of the hydrogen barrier liner; and

at least one tungsten contact connecting the first metal layer and at least one of the source and the drain.

7. The chip of claim 6 , wherein the hydrogen barrier liner includes at least one of:

an iridium oxide and iridium layer, a titanium layer over the iridium oxide and iridium layer, and a second aluminum oxide layer over the titanium layer; or a platinum layer, a titanium layer over the platinum layer, and a second aluminum oxide layer over the titanium layer.

8. The chip of claim 6 , wherein the first metal layer includes a metal wire, wherein the metal wire includes copper or aluminum.

9. The chip of claim 6 , wherein the first metal layer includes a liner and a metal wire over the liner, the liner including a titanium layer, a tantalum nitrite layer over the titanium layer, and a tantalum layer over the tantalum nitrite layer.

10. The chip of claim 6 , further comprising:

a layer of second metal over the silicon dioxide plug, the layer of second metal including a titanium nitride layer and a titanium layer over the titanium nitride layer.

11. A ferro-electric random access memory (FRAM) chip, comprising:

a substrate;

a first dielectric layer over the substrate;

a gate over the first dielectric layer;

a first aluminum oxide layer over the first dielectric layer and the gate;

a second dielectric layer over the first aluminum oxide layer;

a trench through the second dielectric layer and the first aluminum oxide layer to the gate;

a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate;

a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench;

a layer of second metal over the silicon dioxide plug, the layer of second metal including a titanium nitride layer; and

a titanium layer over the titanium nitride layer.

12. The chip of claim 11 , wherein the hydrogen barrier liner includes at least one of:

an iridium oxide and iridium layer, a second titanium layer over the iridium oxide and iridium layer, and a second aluminum oxide layer over the second titanium layer; or a platinum layer, a second titanium layer over the platinum layer, and a second aluminum oxide layer over the second titanium layer.

13. The chip of claim 11 , further comprising:

a source and a drain within the substrate;

a first metal layer partially over the second dielectric layer, over the silicon dioxide plug, and contacting a portion of the hydrogen barrier liner; and

at least one tungsten contact connecting the first metal layer and at least one of the source and the drain.

14. The chip of claim 13 , wherein the first metal layer includes a metal wire, wherein the metal wire includes copper or aluminum.

15. The chip of claim 13 , wherein the first metal layer includes a liner and a metal wire over the liner, the liner including a second titanium layer, a tantalum nitrite layer over the second titanium layer, and a tantalum layer over the tantalum nitrite layer.