Calibrating resistance for integrated circuit

1. An integrated circuit comprising:

a first on-die termination (ODT) configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance value; and

an input buffer configured to receive the pull-up code and the pull-down code, and drive input data by buffering the data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code.

2. The integrated circuit of claim 1 , wherein the first on-die termination (ODT) unit comprising:

a pull-up driving section configured to pull-up drive a first line according to a resistance value which is set depending on the pull-up code; and

a pull-down driving section configured to pull-down drive the first line according to a resistance value which is set depending on the pull-down code.

3. The integrated circuit of claim 1 , wherein the input buffer comprises:

a voltage supply unit configured to supply a power supply voltage through a plurality of switches which are selectively turned on in response to the pull-up code;

a current mirror unit configured to be supplied with the power supply voltage from the voltage supply unit and operate as a constant current source;

a signal input unit coupled to the constant current source and configured to receive the reference voltage and the data and determine a level of the input data; and

a discharge unit configured to determine an amount of charge discharged from the signal input unit in response to the pull-down code.

4. The integrated circuit of claim 1 , further comprising:

a first comparator configured to compare a level of a signal of a first pad, to which an external resistor is coupled, with a level of a ZQ reference voltage and generate a first comparison signal;

a first counter configured to count the pull-up code in response to the first comparison signal;

a driving section configured to drive the first pad in response to the pull-up code; a second comparator configured to compare a level of a driving signal with a level of the ZQ reference voltage and generate a second comparison signal; and

a second counter configured to count the pull-down code in response to the second comparison signal.

5. The integrated circuit of claim 4 , wherein the driving signal is produced by at least one of a pull-up section or a pull-down section.

6. The integrated circuit of claim 1 , further comprising a second ODT unit configured to receive the pull-up code and the pull-down code and adjust a resistance value.

7. The integrated circuit of claim 6 , wherein the resistance values of the first ODT unit and the second ODT unit are equally adjusted in response to the pull-up code and the pull-down code.

8. The integrated circuit of claim 6 , wherein the second ODT unit comprises:

a pull-up driving section configured to pull-up drive a second line, through which the reference voltage is transferred, according to a resistance value which is set depending on the pull-up code; and

a pull-down section configured to pull-down drive the second line according to a resistance value which is set depending on the pull-down code.

9. The integrated circuit of claim 1 , further comprising a reference voltage generation circuit configured to divide a power supply voltage and generate the reference voltage.

10. An integrated circuit comprising: a first on-die termination (ODT) unit configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line, and adjust resistance values of a first pull-up driving section and a first pull-down driving section; a second line for transferring a reference voltage to an input buffer; and a second ODT unit configured to adjust a second pull-up driving section and a second pull-down driving section which drives a voltage at the second line in response to the pull-up code and the pull-down code.

11. The integrated circuit of claim 10 , wherein the first pull-up driving section is configured to pull-up drive the first line according to a resistance value which is set depending on the pull-up code.

12. The integrated circuit of claim 10 , wherein the first pull-down driving section is configured to pull-down drive the first line according to a resistance value which is set depending on the pull-down code.

13. The integrated circuit 10 , wherein the second pull-up driving section is configured to pull-up drive a second line according to a resistance value which is set depending on the pull-up code.

14. The integrated circuit of claim 10 , wherein the second pull-down driving section is configured to pull-down drive a second line according to a resistance value which is set depending on the pull-down code.

15. The integrated circuit of claim 10 , further comprising an input buffer configured to drive input data by buffering data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code, and wherein the data is applied from a memory control and transferred through a first line, and wherein the reference voltage is transferred through a second line.

16. The integrated circuit of claim 15 , wherein the input buffer comprises:

a voltage supply unit configured to supply a power supply voltage through a plurality of switches which are selectively turned on in response to the pull-up code;

a current mirror unit configured to be supplied with the power supply voltage from the voltage supply unit and operate as a constant current source;

a signal input unit coupled to the constant current source and configured to receive the reference voltage and the data and determine a level of the input data; and

a discharge unit configured to determine an amount of charges discharged from the signal input unit in response to the pull-down code.

17. The integrated circuit of claim 10 , further comprising:

a first comparator configured to compare a level of a signal of a first pad, to which an external resistor is coupled, with a level of a ZQ reference voltage and generate a first comparison signal;

a first counter configured to count the pull-up code in response to the first comparison signal;

a driving section configured to drive the first pad in response to the pull-up code; a second comparator configured to compare a level of a driving signal of with a level of the ZQ reference voltage and generate a second comparison signal; and

a second counter that counts the pull-down code in response to the second comparison signal.

18. The integrated circuit of claim 17 , wherein the driving signal is produced by at least one of a pull-up section or a pull-down section.

19. The integrated circuit of claim 10 , wherein the resistance values of the first ODT unit and the second ODT unit are equally adjusted in response to the pull-up code and the pull-down code.

20. The integrated circuit of claim 10 , further comprising a reference voltage generation circuit that divides a power supply voltage and generate the reference voltage.