Controller, storage device, and method for power throttling memory operations
View Patent ↗The embodiments described herein provide a controller, storage device, and method for power throttling memory operations. In one embodiment, a controller is provided in a storage device with a plurality of flash memory devices. The controller determines how much power will be consumed (or heat will be generated) by each of a plurality of commands and dynamically alters when each of the commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed (or heat will be generated), so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time (or a predetermined temperature). In some embodiments, the storage device also has a thermal sensor, and a reading from the thermal sensor can be used, instead of or in addition to the power or thermal costs of each command, to dynamically alter when the commands are performed.
1. A controller comprising:
a first interface through which to communicate with a host;
a second interface through which to communicate with a plurality of flash memory devices;
a memory; and
a processor in communication with the first and second interfaces and the memory, wherein the processor is operative to:
store, in the memory, a plurality of commands to be performed by the plurality of flash memory devices;
determine how much power will be consumed by each of the plurality of commands; and
dynamically alter when each of the plurality of commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time.
2. The controller of claim 1 , wherein the processor dynamically alters when each of the plurality of commands is performed by staggering issuance of the plurality of commands.
3. The controller of claim 2 , wherein the plurality of commands comprises a plurality of program commands, and wherein the processor staggers issuance of the plurality of program commands to limit a simultaneous peak current consumption.
4. The controller of claim 1 , wherein the processor receives the plurality of commands in a certain order and dynamically alters when each of the plurality of commands is performed by re-ordering the plurality of commands.
5. The controller of claim 4 , wherein the plurality of commands comprises a plurality of program commands, and wherein the processor re-orders the plurality of program commands to minimize peak power.
6. The controller of claim 1 , wherein the processor dynamically alters when each of the plurality of commands is performed by staggering issuance of read commands based on an error correction code (ECC) rate.
7. The controller of claim 1 , wherein the plurality of commands comprises a plurality of background commands, and wherein the processor modulates performance of the background commands according to a volume of incoming host commands.
8. The controller of claim 1 , wherein the plurality of commands comprises a plurality of background commands, and wherein the processor modulates performance of the background commands according to thermal stress.
9. The controller of claim 7 or 8 , wherein at least one background command comprises a copy command, a move command, a data scrambling command, a column replacement command, a command to handle write aborts and/or program failures (via safe zones), a read scrubbing command, a wear leveling command, a bad block and/or spare block management command, an error detection code (EDC) command, a status command, an encryption command, an error recovery command, and an address mapping command.
10. The controller of claim 1 , wherein the processor is further operative to receive a temperature reading from a thermal sensor, and wherein the processor uses both the temperature reading and the determination of how much power will be consumed in deciding how to dynamically alter when each of the plurality of commands is performed.
11. The controller of claim 1 , wherein at least one of the plurality of flash memory devices comprises a three-dimensional memory array.
12. The controller of claim 11 , wherein the three-dimensional memory array is a passive element array.
13. The controller of claim 11 , wherein word lines and/or bit lines in the three-dimensional memory array are shared between levels.
14. A storage device comprising:
a plurality of flash memory devices;
a thermal sensor; and
a controller in communication with the plurality of flash memory devices and the thermal sensor, wherein the controller comprises a memory and a processor operative to:
store, in the memory, a plurality of commands to be performed by the plurality of flash memory devices;
receive a temperature reading from the thermal sensor; and
dynamically alter when each of the plurality of commands operating on one or more of the flash memory devices is performed based on the temperature reading from the thermal sensor so that performance of the plurality of commands does not exceed at least one of a predetermined average power limit over a period of time and a predetermined temperature.
15. The storage device of claim 14 , wherein the processor dynamically alters when each of the plurality of commands is performed by staggering issuance of the plurality of commands.
16. The storage device of claim 15 , wherein the plurality of commands comprises a plurality of program commands, and wherein the processor staggers issuance of the plurality of program commands to limit a simultaneous peak current consumption.
17. The storage device of claim 14 , wherein the processor receives the plurality of commands in a certain order and dynamically alters when each of the plurality of commands is performed by re-ordering the plurality of commands.
18. The storage device of claim 17 , wherein the plurality of commands comprises a plurality of program commands, and wherein the processor re-orders the plurality of program commands to minimize peak power.
19. The storage device of claim 14 , wherein the processor dynamically alters when each of the plurality of commands is performed by staggering issuance of read commands based on an error correction code (ECC) rate.
20. The storage device of claim 14 , wherein the plurality of commands comprises a plurality of background commands, and wherein the processor modulates performance of the background commands according to a volume of incoming host commands.
21. The storage device of claim 14 , wherein the plurality of commands comprises a plurality of background commands, and wherein the processor modulates performance of the background commands according to thermal stress.
22. The storage device of claim 20 or 21 , wherein at least one background command comprises a copy command, a move command, a data scrambling command, a column replacement command, a command to handle write aborts and/or program failures (via safe zones), a read scrubbing command, a wear leveling command, a bad block and/or spare block management command, an error detection code (EDC) command, a status command, an encryption command, an error recovery command, and an address mapping command.
23. The storage device of claim 14 , wherein the processor is further operative to determine how much power will be consumed by each of the plurality of commands and wherein the processor uses both the temperature reading and the determination of how much power would be consumed in deciding how to dynamically alter when each of the plurality of commands is performed.
24. The storage device of claim 14 , wherein the thermal sensor is in the controller.
25. The storage device of claim 14 , wherein the thermal sensor is in one of the flash memory devices.
26. The storage device of claim 14 , wherein at least one of the plurality of flash memory devices comprises a three-dimensional memory array.
27. The storage device of claim 26 , wherein the three-dimensional memory array is a passive element array.
28. The storage device of claim 26 , wherein word lines and/or bit lines in the three-dimensional memory array are shared between levels.
29. A controller comprising:
a first interface through which to communicate with a host;
a second interface through which to communicate with a plurality of flash memory devices;
a memory; and
a processor in communication with the first and second interfaces and the memory, wherein the processor is operative to:
store, in the memory, a plurality of commands to be performed by the plurality of flash memory devices;
determine how much heat would be generated by each of the plurality of commands; and
dynamically alter when each of the plurality of commands operating on one or more of the flash memory devices is performed based on the determination of how much heat would be generated so that performance of the plurality of commands does not exceed a predetermined temperature.
30. The controller of claim 29 , wherein the processor dynamically alters when each of the plurality of commands is performed by staggering issuance of the plurality of commands.
31. The controller of claim 29 , wherein the processor receives the plurality of commands in a certain order and dynamically alters when each of the plurality of commands is performed by re-ordering the plurality of commands.
32. The controller of claim 29 , wherein the processor dynamically alters when each of the plurality of commands is performed by staggering issuance of read commands based on an error correction code (ECC) rate.
33. The controller of claim 29 , wherein the plurality of commands comprises a plurality of background commands, and wherein the processor modulates performance of the background commands according to a volume of incoming host commands.
34. The controller of claim 33 , wherein at least one background command comprises a copy command, a move command, a data scrambling command, a column replacement command, a command to handle write aborts and/or program failures (via safe zones), a read scrubbing command, a wear leveling command, a bad block and/or spare block management command, an error detection code (EDC) command, a status command, an encryption command, an error recovery command, and an address mapping command.
35. The controller of claim 29 , wherein at least one of the plurality of flash memory devices comprises a three-dimensional memory array.
36. The controller of claim 35 , wherein the three-dimensional memory array is a passive element array.
37. The controller of claim 35 , wherein word lines and/or bit lines in the three-dimensional memory array are shared between levels.