Flushed data alignment with physical structures
A method and system are disclosed herein for performing operations on a parallel programming unit in a memory system. The parallel programming unit includes multiple physical structures (such as memory cells in a row) in the memory system that are configured to be operated on in parallel. The method and system perform a first operation on the parallel programming unit, the first operation operating on only part of the parallel programming unit and not operating on a remainder of the parallel programming unit, set a pointer to indicate at least one physical structure in the remainder of the parallel programming unit, and perform a second operation using the pointer to operate on no more than the remainder of the parallel programming unit. In this way, the method and system may realign programming to the parallel programming unit when partial writes to the parallel programming unit occur.
1. A method of performing operations on a parallel programming unit in a memory system, the method comprising the memory system:
performing a first operation on the parallel programming unit, the parallel programming unit comprising multiple physical structures configured to be operated on in parallel, the first operation operating on only some of the multiple physical structures in the parallel programming unit and not operating on a remainder of the parallel programming unit;
setting a pointer to indicate at least one physical structure in the remainder of the parallel programming unit; and
performing a second operation using the pointer to operate on no more than the remainder of the parallel programming unit by writing only to memory cells in a row, as indicated by the pointer, from a column, as indicated by the pointer, to an end of the row.
2. The method of claim 1 , wherein the first operation comprises a cache flushing operation.
3. The method of claim 1 , wherein the parallel programming unit comprises a row of memory cells.
4. The method of claim 3 , wherein the pointer indicates a first cell not operated on in the first operation.
5. The method of claim 4 , wherein the column of the pointer indicates a number of the remainder of the parallel programming unit.
6. The method of claim 1 , wherein the first operation and second operation are write operations.
7. The method of claim 6 , further comprising iteratively writing, after performing the second operation, to the remainder of the parallel programming unit until all of the remainder is written to.
8. The method of claim 1 , wherein the parallel programming unit comprises all physical structures in the memory system that can be programmed or read in parallel and can be programmed or read with a same or similar completion time.
9. A storage device comprising:
a non-volatile memory comprising parallel programmable units, the parallel programming units comprising multiple physical structures configured to be operated on in parallel; and
a controller in communication with the non-volatile memory, the controller configured to:
perform a first operation on the parallel programming unit, the first operation operating on only some of the multiple physical structures in the parallel programming unit and not operating on a remainder of the parallel programming unit;
set a pointer to indicate at least one physical structure in the remainder of the parallel programming unit; and
perform a second operation using the pointer to operate on no more than the remainder of the parallel programming unit by writing only to memory cells in a row, as indicated by the pointer, from a column, as indicated by the pointer, to an end of the row.
10. The storage device of claim 9 , wherein the first operation comprises a cache flushing operation.
11. The storage device of claim 9 , wherein the parallel programming unit comprises a row of the memory cells.
12. The storage device of claim 11 , wherein the pointer is configured to indicate a first cell not operated on in the first operation.
13. The storage device of claim 12 , wherein the column of the pointer is configured to indicate a number of the remainder of the parallel programming unit.
14. The storage device of claim 13 , wherein the first operation and second operation are write operations.
15. The storage device of claim 14 , wherein the controller is further configured to iteratively write, after performing the second operation, to the remainder of the parallel programming unit until all of the remainder is written to.
16. The storage device of claim 9 , wherein the parallel programming unit comprises all physical structures in the memory system that can be programmed or read in parallel and can be programmed or read with a same or similar completion time.