Data storage device and method to correct bit values using multiple read voltages

1. A method comprising:

in a data storage device including a controller, the data storage device coupled to a three-dimensional (3D) memory, performing:

causing a group of storage elements to be sensed using a first read voltage to obtain a first plurality of bit values;

initiating an error correction code (ECC) procedure on the first plurality of bit values; and

in response to the ECC procedure indicating that the first plurality of bit values is uncorrectable by the ECC procedure:

causing the group of the storage elements to be sensed using a second read voltage to obtain a second plurality of bit values;

comparing the first plurality of bit values with the second plurality of bit values to identify a first set of bits having different values in the first plurality of bit values as compared to the second plurality of bit values; and

changing one or more values of the first plurality of bit values for one or more bits in the first set of bits to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values.

2. The method of claim 1 , further comprising initiating a second ECC procedure on the first plurality of corrected bit values.

3. The method of claim 2 , further comprising, in response to the second ECC procedure on the first plurality of corrected bit values indicating that the first plurality of corrected bit values is uncorrectable by the second ECC procedure:

causing the group of the storage elements to be sensed using a third read voltage to obtain a third plurality of bit values;

comparing the third plurality of bit values with the first plurality of bit values and the second plurality of bit values to identify a second set of bits having different values in at least one of the first plurality of bit values, the second plurality of bit values, and the third plurality of bit values; and

changing a bit value of each of the one or more bits of the second identified set of bits to a majority value of the different values sensed in the first plurality of bit values, the second plurality of bit values, and the third plurality of bit values to generate a second plurality of corrected bit values.

4. The method of claim 3 , further comprising:

initiating a third ECC procedure on the second plurality of corrected bit values; and

in response to the third ECC procedure on the second plurality of corrected bit values indicating that the second plurality of corrected bit values is not correctable:

causing the group of the storage elements to be sensed using one or more additional read voltages to obtain one or more additional sets of bit values; and

changing one or more of the bit values to a majority value of corresponding different values sensed in the first plurality of bit values, the second plurality of bit values, the third plurality of bit values, and the one or more additional sets of bit values.

5. The method of claim 1 , further comprising maintaining a table of read voltages, wherein the second read voltage is retrieved from the table.

6. The method of claim 5 , wherein the second read voltage is greater than the first read voltage in response to determining that one or more bits of the identified first set of bits includes at least one bit suspected to be changed by a programming disturbance.

7. The method of claim 5 , wherein the second read voltage is less than the first read voltage in response to determining that one or more bits of the identified first set of bits includes at least one bit suspected to be changed by a retention error.

8. The method of claim 1 , wherein the data storage device includes a read result storage area configured to store the first plurality of bit values and the second plurality of bit values.

9. The method of claim 1 , wherein comparing the first plurality of bit values with the second plurality of bit values includes performing an exclusive-OR operation.

10. The method of claim 1 , wherein the ECC procedure includes one of:

a Reed-Solomon ECC procedure; and

a Bose-Chaudhuri-Hocquenghem (BCH) ECC procedure.

11. An apparatus comprising:

a non-volatile three-dimensional (3D) memory; and

a controller of a data storage device, the data storage device coupled to the non-volatile 3D memory, wherein the controller is configured to initiate a first error correction code (ECC) procedure on a first plurality of bit values read from a group of storage elements using a first read voltage, and in response to the first ECC procedure determining that the first plurality of bit values is not correctable, the controller is further configured to:

cause the group of the storage elements to be sensed using a second read voltage to obtain a second plurality of bit values;

compare the first plurality of bit values with the second plurality of bit values to identify a first set of bits having different values in the first plurality of bit values as compared to the second plurality of bit values; and

change one or more values of the first plurality of bit values for one or more bits in the first set of bits to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values.

12. The apparatus of claim 11 , wherein the controller is further configured to initiate a second ECC procedure on the first plurality of corrected bit values.

13. The apparatus of claim 12 , wherein the controller is further configured, in response to the second ECC procedure on the first plurality of corrected bit values indicating that the first plurality of corrected bit values is not correctable by the second ECC procedure, to:

cause the group of the storage elements to be sensed using a third read voltage to obtain a third plurality of bit values;

compare the third plurality of bit values with the first plurality of bit values and the second plurality of bit values to identify a second set of bits having different values in at least one of the first plurality of bit values, the second plurality of bit values, and the third plurality of bit values; and

change a bit value of at least one of the one or more bits of the second identified set of bits to a majority value of the different values sensed in the first plurality of bit values, the second plurality of bit values, and the third plurality of bit values to generate a second plurality of corrected bit values.

14. The apparatus of claim 13 , wherein the controller is further configured to:

initiate a third ECC procedure on the second plurality of corrected bit values; and

in response to the third ECC procedure on the second plurality of corrected bit values indicating that the second plurality of corrected bit values is not correctable:

cause the group of the storage elements to be sensed using one or more additional read voltages to obtain one or more additional sets of bit values; and

change one or more of the bit values to a majority value of corresponding different values sensed in the first plurality of bit values, the second plurality of bit values, the third plurality of bit values, and the one or more additional sets of bit values.

15. The apparatus of claim 11 , wherein the controller is further configured to retrieve the second read voltage from a table of read voltages maintained by the controller.

16. The apparatus of claim 15 , wherein the second read voltage is greater than the first read voltage in response to the controller determining that one or more bits of the identified first set of bits includes at least one bit suspected to be changed by a programming disturbance.

17. The apparatus of claim 15 , wherein the second read voltage is less than the first read voltage in response to the controller determining that one or more bits of the identified first set of bits includes at least one bit suspected to be changed by a retention error.

18. The apparatus of claim 11 , further comprising a read result storage area to store the first plurality of bit values and the second plurality of bit values.

19. The apparatus of claim 11 , wherein the controller is configured to compare the first plurality of bit values with the second plurality of bit values by performing an exclusive-OR operation.