IP Library Granted Patent US 9,024,790
Granted Patent B2
US 9,024,790 · App. 13/347,312 · Granted May 5, 2015

Capacitive keyboard with non-locking reduced keying ambiguity

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Quick Facts
Patent No.
US 9,024,790
App. No.
13/347,312
Granted
May 5, 2015
Kind
B2
Abstract

Keyboards, keypads and other data entry devices can suffer from a keying ambiguity problem. In a small keyboard, for example, a user's finger is likely to overlap from a desired key to onto adjacent ones. An iterative method of removing keying ambiguity from a keyboard comprising an array of capacitive keys involves measuring a signal strength associated with each key in the array, comparing the measured signal strengths to find a maximum, determining that the key having the maximum signal strength is the unique user-selected key, and maintaining that selection until either the initially selected key's signal strength drops below some threshold level or a second key's signal strength exceeds the first key's signal strength.

Claims (39)

1. An apparatus comprising:

plurality of keys;

control logic operatively coupled to the plurality of keys and configured to:

analyze, to determine a first active key, respective first signal values of the plurality of keys;

assign, based at least on the respective first sensor values of the plurality keys, a first key as the first active key; and

analyze, to determine a second active key, respective second signal values of the plurality of keys, the analysis, to determine the second active key, of the respective second signal values of the plurality of keys being biased in favor of the first key.

2. The apparatus of claim 1 , wherein each key comprises a respective capacitive proximity sensor.

3. The apparatus of claim 1 , wherein at least one key of the plurality of keys comprises a guard ring disposed around at least another key of the plurality of keys.

4. The apparatus of claim 1 , wherein the control logic is configured to bias the analysis, to determine the second active key, of the respective second signal values of the plurality of keys in favor of the first key by increasing the respective sensor value associated with the first key.

5. The apparatus of claim 1 , wherein each of the plurality of keys has an associated counter and the control logic is configured to bias the analysis, to determine the second active key, of the respective second signal values of the plurality of keys in favor of the first key by changing a value stored in at least one of the counters.

6. The apparatus of claim 1 , wherein the control logic comprises a microcontroller.

7. A method comprising:

analyzing, to determine a first active key, respective first sensor values of a plurality of keys;

assigning, based at least on the respective sensor values of the plurality keys, a first key as the first active key; and

analyzing, to determine a second active key, respective second signal values of the plurality of keys, the analysis, to determine the second active key, of the respective second signal values of the plurality of keys being biased in favor of the first key.

8. The method of claim 7 , wherein the respective sensor values are representative of a respective capacitance of a respective key of the plurality of keys.

9. The method of claim 7 , wherein at least one key of the plurality of keys comprises a guard ring disposed about at least one other key of the plurality of keys.

10. The method of claim 7 , comprising biasing the analysis, to determine the second active key, of the respective second signal values of the plurality of keys in favor of the first key by increasing the respective sensor value of the first key.

11. The method of claim 7 , comprising decreasing, when analyzing, to determine a second active key, respective second signal values of the plurality of keys, the respective sensor values associated with each of the keys other than the first key.

12. The method of claim 7 , wherein each key of the plurality of keys has an associated counter and biasing the analysis, to determine the second active key, of the respective second signal values of the plurality of keys in favor of the first key comprises changing a value stored in at least one of the counters.

13. Logic embodied in a non-transitory computer-readable medium, the logic configured when executed to perform operations comprising:

analyzing, to determine a first active key, respective first sensor values of a plurality of keys;

assigning, based at least on the respective sensor values of the plurality keys, a first key as the first active key; and

analyzing, to determine a second active key, respective second signal values of the plurality of keys, the first key being biased during the analysis, the analysis, to determine the second active key, of the respective second signal values of the plurality of keys being biased in favor of the first key.

14. The logic of claim 13 , wherein the respective sensor values are representative of a respective capacitance of a respective key of the plurality of keys.

15. The logic of claim 13 , wherein at least one key of the plurality of keys comprises a guard ring disposed about at least one other of key of the plurality keys.

16. The logic of claim 13 , comprising biasing the analysis, to determine the second active key, of the respective second signal values of the plurality of keys in favor of the first key by increasing the respective sensor value of the first key.

17. The logic of claim 13 , configured when executed to perform operations comprising decreasing, when analyzing, to determine a second active key, respective second signal values of the plurality of keys, the respective sensor values associated with all each of the keys other than the first key.

18. The logic of claim 13 , wherein each key of the plurality of keys has an associated counter and biasing the analysis, to determine the second active key, of the respective second signal values of the plurality of keys in favor of the first key comprises changing a value stored in at least one of the counters.

19. The apparatus of claim 1 , wherein the control logic is configured to assign the first key as the second active key.

20. The apparatus of claim 1 , wherein the control logic is configured to assign, based at least on respective first sensor values of the plurality keys, the first key as the first active key based on:

the respective first sensor value of the first key exceeding a threshold; and

the respective first sensor value of the first key exceeding the respective sensor values of the other keys in the plurality of keys.

21. The apparatus of claim 1 , wherein the control logic is configured to assign, based at least on respective second sensor values of the plurality keys, a second key as the second active key based at least on the respective second sensor value of the second key exceeding the respective second sensor value of the first active key by a particular amount, the first key and the second key being different keys.

22. The method of claim 7 , comprising assigning the first key as the second active key.

23. The method of claim 7 , comprising assigning, based at least on respective first sensor values of the plurality keys, the first key as the first active key based on:

the respective first sensor value of the first key exceeding a threshold; and

the respective first sensor value of the first key exceeding the respective sensor values of the other keys in the plurality of keys.

24. The method of claim 7 , comprising assigning, based at least on respective second sensor values of the plurality keys, a second key as the second active key based at least on the respective second sensor value of the second key exceeding the respective second sensor value of the first active key by a particular amount, the first key and the second key being different keys.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2019
From: MICROCHIP TECHNOLOGY INC.; ATMEL CORPORATION; MICROCHIP TECHNOLOGY GERMANY GMBH
To: NEODRÓN LIMITED
Reel/Frame 048259/0840 →
RELEASE OF SECURITY INTEREST IN CERTAIN PATENT RIGHTS Recorded Dec 21, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 047976/0884 →
RELEASE OF SECURITY INTEREST IN CERTAIN PATENT RIGHTS Recorded Dec 21, 2018
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 047976/0937 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2013
From: QRG LIMITED
To: ATMEL CORPORATION
Reel/Frame 030145/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2013
From: PHILIPP, HARALD
To: QRG LIMITED
Reel/Frame 030145/0194 →