IP Library Granted Patent US 8,344,450
Granted Patent B2
US 8,344,450 · App. 13/541,213 · Granted Jan 1, 2013

Semiconductor device with buried bit lines and method for fabricating the same

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Quick Facts
Patent No.
US 8,344,450
App. No.
13/541,213
Granted
Jan 1, 2013
Kind
B2
Abstract

A semiconductor device includes: a semiconductor substrate configured to include a plurality of trenches therein; a plurality of buried bit lines each configured to fill a portion of each trench; a plurality of active pillars each formed in an upper portion of each buried bit line; a plurality of vertical gates each configured to surround each active pillar; and a plurality of word lines configured to couple neighboring vertical gates with each other.

Claims (17)

1. A semiconductor device, comprising:

a semiconductor substrate configured to include a plurality of trenches therein;

a plurality of buried bit lines each configured to fill a portion of each trench;

a plurality of active pillars each formed in an upper portion of each buried bit line;

a plurality of vertical gates each configured to surround each active pillar; and

a plurality of word lines configured to couple neighboring vertical gates with each other.

2. The semiconductor device of claim 1 , further comprising:

an ohmic contact layer interposed between the plurality of the buried bit lines and the plurality of the active pillars.

3. The semiconductor device of claim 2 , wherein the ohmic contact layer comprises a metal silicide layer.

4. The semiconductor device of claim 1 , wherein each of the plurality of the active pillars comprises:

a first active pillar electrically connected to each buried bit line; and

a second active pillar formed on both sidewalls of each first active pillar.

5. The semiconductor device of claim 4 , wherein the first active pillar is a silicon epitaxial layer, and the second active pillar is of the same material as a material of the semiconductor substrate.

6. The semiconductor device of claim 1 , wherein each of the plurality of the trenches comprises:

a first trench; and

a second trench configured to be coupled with a lower portion of the first trench and have a longer line width than a line width of the first trench.

7. The semiconductor device of claim 6 , wherein the plurality of the buried bit lines fill the plurality of the second trenches.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 14, 2024
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067412/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067369/0832 →
CHANGE OF NAME Recorded May 6, 2024
From: HYNIX-SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067328/0814 →