Semiconductor device with buried bit lines and method for fabricating the same
View Patent ↗A semiconductor device includes: a semiconductor substrate configured to include a plurality of trenches therein; a plurality of buried bit lines each configured to fill a portion of each trench; a plurality of active pillars each formed in an upper portion of each buried bit line; a plurality of vertical gates each configured to surround each active pillar; and a plurality of word lines configured to couple neighboring vertical gates with each other.
1. A semiconductor device, comprising:
a semiconductor substrate configured to include a plurality of trenches therein;
a plurality of buried bit lines each configured to fill a portion of each trench;
a plurality of active pillars each formed in an upper portion of each buried bit line;
a plurality of vertical gates each configured to surround each active pillar; and
a plurality of word lines configured to couple neighboring vertical gates with each other.
2. The semiconductor device of claim 1 , further comprising:
an ohmic contact layer interposed between the plurality of the buried bit lines and the plurality of the active pillars.
3. The semiconductor device of claim 2 , wherein the ohmic contact layer comprises a metal silicide layer.
4. The semiconductor device of claim 1 , wherein each of the plurality of the active pillars comprises:
a first active pillar electrically connected to each buried bit line; and
a second active pillar formed on both sidewalls of each first active pillar.
5. The semiconductor device of claim 4 , wherein the first active pillar is a silicon epitaxial layer, and the second active pillar is of the same material as a material of the semiconductor substrate.
6. The semiconductor device of claim 1 , wherein each of the plurality of the trenches comprises:
a first trench; and
a second trench configured to be coupled with a lower portion of the first trench and have a longer line width than a line width of the first trench.
7. The semiconductor device of claim 6 , wherein the plurality of the buried bit lines fill the plurality of the second trenches.