IP Library Granted Patent US 9,006,703
Granted Patent B2
US 9,006,703 · App. 13/955,531 · Granted Apr 14, 2015

Method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof

Inventors: Shawn A. Adderly (Essex Junction, VT); Brian M. Czabaj (Essex Junction, VT); Daniel A. Delibac (Colchester, VT); Jeffrey P. Gambino (Westford, VT); Matthew D. Moon (Jeffersonville, VT); David C. Thomas (Richmond, VT)
Assignee: International Business Machines Corporation
H01L28/40H01L22/12
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Quick Facts
Patent No.
US 9,006,703
App. No.
13/955,531
Granted
Apr 14, 2015
Kind
B2
Abstract

Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

Claims (18)

1. A method comprising:

removing a portion of a first lateral extrusion in an aluminum layer of a semiconductor structure;

determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer subsequent to the removing of the portion of the first lateral extrusion; and

determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

2. The method of claim 1 , wherein the removing of the portion of the first lateral extrusion includes performing a dry etching process on the portion of the first lateral extrusion.

3. The method of claim 2 , wherein the dry etching process includes a reactive-ion etching.

4. The method of claim 1 , wherein the semiconductor structure further includes:

a metallurgy stack including the first lateral extrusion in the aluminum layer;

a metal-insulator-metal capacitor (MIM capacitor) structure positioned adjacent the metallurgy stack; and

an opening extending through the metallurgy stack, the opening surrounding the MIM capacitor structure.

5. The method of claim 4 , wherein the removing of the portion of the first lateral extrusion includes removing the portion of the first lateral extrusion a first predetermined distance from the metallurgy stack of the semiconductor structure.

6. The method of claim 4 , wherein the first lateral extrusion in the aluminum layer extends into the opening.

7. The method of claim 5 , wherein the removing of the portion of the first lateral extrusion includes removing the portion of the first lateral extrusion a second predetermined distance from the MIM capacitor structure of the semiconductor structure.

8. The method of claim 4 , wherein the MIM capacitor structure includes a second lateral extrusion extending into the opening.

9. The method of claim 7 , further comprising removing a portion of the second lateral extrusion a third predetermined distance from the MIM capacitor structure of the semiconductor structure.

10. The method of claim 9 , wherein the removing of the portion of the second lateral extrusion includes removing the portion of the second lateral extrusion a fourth predetermined distance from the metallurgy stack of the semiconductor structure.

11. The method of claim 1 , further comprising providing an indicator of an electrical fault in the semiconductor structure in response to the determined difference between the post-removal thickness and the pre-removal thickness of the dielectric layer exceeding a predetermined condition threshold.

12. The method of claim 11 , wherein the predetermined condition threshold is based upon at least one of the pre-removal thickness of the dielectric layer, and a material composition of the dielectric layer of the semiconductor structure.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2013
From: ADDERLY, SHAWN A.; CZABAJ, BRIAN M.; DELIBAC, DANIEL A.; GAMBINO, JEFFREY P.; MOON, MATTHEW D.; THOMAS, DAVID C.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 030914/0822 →
Continuity (1)
Related Publication 20150035117A1 · Feb 5, 2015