IP Library Granted Patent US 9,507,680
Granted Patent B2
US 9,507,680 · App. 14/222,918 · Granted Nov 29, 2016

Verification system and method for automated verification of register information for an electronic system

Inventors: Michael Rohleder (Unterschleissheim, DE); Glen Nicholas Mithran Evans (Austin, TX); Bridget Catherine Hooser (Munich, DE); Carmen Klug-Mocanu (Aying, DE)
Assignee: Freescale Semiconductor, Inc.
G06F11/261
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Quick Facts
Patent No.
US 9,507,680
App. No.
14/222,918
Granted
Nov 29, 2016
Kind
B2
Abstract

A system for verifying register information includes a design database containing a description of the electronic system, a register description database containing register information relating to the electronic system, a customization information module for storing a customization information extracted from the design database and a simulator which is arranged to execute verification stimuli in accordance with at least one check function and to generate a verification result. Verification stimuli are generated by combining register information with customization information. A mismatch between the expected and actual register implementation is recorded and the register in question identified. This permits corrections to be applied as appropriate to the document database or to the register description database. The corrected register description database may be used in a document generation process to produce an up-to-date reference manual for the electronic system.

Claims (29)

1. A verification system for automated verification of register information for an electronic system, the verification system comprising:

a design database containing a description of the electronic system,

a register description database containing a behavioural description of registers,

a customization information database for storing customization information specific to a particular version of the electronic system,

a stimulus generator arranged to generate verification stimuli by combining information stored in the register description database with customization information,

a check function database,

a simulator operably coupled to the design database and arranged to execute said verification stimuli in accordance with at least one check function from the check function database and arranged to generate a simulation result,

a mismatch identification module arranged to evaluate the simulation result and to identify a mismatch between an expected behaviour of a register access and an actual behaviour of said register access and arranged to enable identification and correction of a root cause of a mismatch within the design database, the customization information database or the register description database,

a document information database containing the behavioral description of registers, wherein the document information database contains register information, the register information comprising the behavioral description of the registers, wherein the register information is enriched with a textual description of functionality controlled by the registers and fields within the registers, and

a document generator for generating documentation based on the behavioural description of the registers, the documentation selected from a group consisting of a user manual and a reference manual, wherein the document generator is configured to generate the documentation based on the behavioral description of the registers contained in the document information database, to combine the register information with the textual description, to format results, and to generate from the results a human readable document.

2. The verification system of claim 1 , wherein a behavioural description of registers is arranged to reflect the register behaviour with respect to memory mapped accesses to the registers of each IP block included in the electronic system described by the design database.

3. The verification system of claim 2 , wherein a behavioural description of registers is arranged to reflect modifications of register behaviour controlled by modifiers provided by the customization information database.

4. The verification system of claim 1 , wherein a behavioural description of registers is arranged to reflect modifications of register behaviour controlled by modifiers provided by the customization information database.

5. The verification system of claim 1 , wherein customization information includes at least one of the following: configuration management information, parameterization information, and connectivity information.

6. The verification system of claim 1 , wherein customization information is arranged to reflect modifiers implemented within a specific electronic system, said modifiers comprising, for any building block comprising the electronic system, at least one of the following:

building block instantiation specific modifiers that are different between multiple instances of the same building block;

building block specific modifiers that are common for all instances of the building block;

building block specific modifiers that select behaviour that is specific to a particular version of a building block; and

building block specific modifiers that remove register or field related features of a building block.

7. The verification system of claim 1 , wherein each check function comprises a sequence of at least one access to a register under test and is arranged to verify one of the features or a particular aspect of a feature in the context of the register under test.

8. The verification system of claim 1 , wherein the mismatch identification module is arranged to identify a mismatch of at least one feature or a particular aspect of a feature, wherein a simulation in the context of the design database exhibits behaviour of a corresponding register that is different from the expected behaviour as described in the register description database taking into account the specific customization as specified in the customization information database.

9. The verification system of claim 1 , wherein the mismatch identification module is arranged to locate a specific form of information record within the simulation result, wherein a record specifies a result of the execution of a check function, wherein data, detailing an identified mismatch, are provided with such information records in cases where an unsuccessful execution has been flagged.

10. The verification system of claim 1 , wherein the mismatch identification module is arranged to identify a failure feature of a block or register by combining the data from the information records of multiple check function executions within a simulation result by evaluating data provided by information records in a certain predefined order, in order to select the failing feature.

11. The verification system of claim 1 wherein the document generator is configured to further generate a header file for usage by a compiler for compiling executable instructions.

12. The verification system of claim 1 wherein the document generator is configured to be in a correction and confirmation loop including the correction of the root cause of the mismatch by the mismatch generator.

13. The verification system of claim 1 wherein the behavioural description of the registers has been proven to match the registers actually being implemented in the electronic system, resulting in the documentation being proved to match the registers actually being implemented in the electronic system.

14. The verification system of claim 1 wherein two register description databases using a machine-readable, structured data format are compared to obtain matching information proven to match the registers.

15. The verification system of claim 14 wherein the machine-readable, structured data format is an extensible markup language (XML).

16. The verification system of claim 1 wherein verification of corresponding register information upon which generation of documentation is based is configured to occur concurrently with development of the electronic system.

Assignments (28)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPLICATION NUMBERS 12222918, 14185362, 14147598, 14185868 & 14196276 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0479. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0498 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBERS PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0438. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0136 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0479 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0438 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0763 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 032845/0497 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0522 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2014
From: ROHLEDER, MICHAEL; EVANS, GLEN NICHOLAS MITHRAN; HOOSER, BRIDGET CATHERINE; KLUG-MOCANU, CARMEN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032506/0229 →
Continuity (1)
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