Patterning multiple, dense features in a semiconductor device using a memorization layer

1. A method of forming a semiconductor device, the method comprising:

providing a stack of layers formed over a set of gate structures, the stack of layers including a dielectric layer over the set of gate structures, a chemical mechanical planarization stop layer (CMPSL) over the dielectric layer, a hardmask over the CMPSL, an etch stop layer over the hardmask, and a memorization layer over the etch stop layer;

patterning a plurality of openings in the memorization layer;

forming a gap-fill material within each of the plurality of openings;

removing the memorization layer;

removing the etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; and

etching the hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer.

2. The method according to claim 1 , further comprising:

etching the semiconductor device to remove the hardmask within each of the set of openings, selective to the CMPSL, and to remove the remaining portion of the etch stop layer; and

forming a set of dummy source/drain (S/D) contact pillars over a set of fins of the semiconductor device by etching the dielectric layer selective to a gate capping layer of each of the set of gate structures.

3. The method according to claim 1 , the forming the gap-fill material comprising:

depositing the gap-fill material over the memorization layer;

etching the gap-fill material to remove the gap-fill material from atop the memorization layer, and to recess the gap-fill material within each of the plurality of openings.

4. The method according to claim 1 , the gap-fill material comprising at least one of: a-C, silicon oxycarbide (SiOC), silicon nitride (SiN), organic planarization layer (OPL), titanium nitride (TiN), high-density plasma (HDP) nitride, deep ultraviolet light absorbing oxide (DUO), and flowable chemical vapor deposition (FCVD) oxide.

5. The method according to claim 1 , the dielectric layer comprising a tetra ethyl ortho silicate (TEOS) layer, the CMPSL comprising nitride, and the etch stop layer comprising silicon oxynitride.

6. The method according to claim 1 , the hardmask comprising an amorphous-carbon (a-C) layer.

7. The method according to claim 1 , the memorization layer comprising one of: TEOS, low temperature oxide (LTO), DUO, a low-temperature a-Si, and poly silicon.

8. The method according to claim 2 , the gate capping layer comprising silicon nitride.

9. A method for patterning multiple, dense features in a semiconductor device using a memorization layer, the method comprising:

providing a stack of layers formed over a set of gate structures, the stack of layers including a dielectric layer over the set of gate structures, a chemical mechanical planarization stop layer (CMPSL) over the dielectric layer, a hardmask over the CMPSL, an etch stop layer over the hardmask, and a memorization layer over the etch stop layer;

patterning a plurality of openings in the memorization layer;

forming a gap-fill material within each of the plurality of openings;

removing the memorization layer;

removing the etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; and

etching the hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer.

10. The method according to claim 9 , further comprising:

etching the semiconductor device to remove the hardmask within each of the set of openings, selective to the CMPSL, and to remove the remaining portion of the etch stop layer; and

forming a set of dummy source/drain (S/D) contact pillars over a set of fins of the semiconductor device by etching the dielectric layer selective to a gate capping layer of each of the set of gate structures.

11. The method according to claim 9 , the forming the gap-fill material comprising:

depositing the gap-fill material over the memorization layer;

etching the gap-fill material to remove the gap-fill material from atop the memorization layer, and to recess the gap-fill material within each of the plurality of openings.

12. The method according to claim 9 , the gap-fill material comprising at least one of: a-C, silicon oxycarbide (SiOC), silicon nitride (SiN), organic planarization layer (OPL), titanium nitride (TiN), high-density plasma (HDP) nitride, deep ultraviolet light absorbing oxide (DUO), and flowable chemical vapor deposition (FCVD) oxide.

13. The method according to claim 9 , the dielectric layer comprising a tetra ethyl ortho silicate (TEOS) layer, the CMPSL comprising nitride, and the etch stop layer comprising silicon oxynitride.

14. The method according to claim 9 , the hardmask comprising an amorphous-carbon (a-C) layer.

15. The method according to claim 9 , the memorization layer comprising one of: TEOS, low temperature oxide (LTO), DUO, a low-temperature a-Si, and poly silicon.

16. The method according to claim 10 , the gate capping layer comprising silicon nitride.