System and method for handling memory repair data
In a system on chip (SOC) device, continuity of a memory repair signature chain, which is accessible by all enabled memory systems, is provided, even when certain memory systems are gated (off) for certain SOC configurations. A mechanism for converting between compressed and uncompressed memory repair data within the repair chain is provided so that memory systems that support either uncompressed memory repair data (such as ternary content addressable memories) or compressed memory repair data can be incorporated in the SOC.
1. An integrated circuit, comprising:
first and second memory systems, wherein each memory system includes a memory module having an associated first repair register for receiving compressed memory repair data, and wherein the first repair registers are connected in series as a chain;
a store for storing compressed memory repair data for the first and second memory modules; and
a processor, operably coupled to the store, for fetching the compressed memory repair data from the store and shifting the fetched compressed memory repair data through the chain for reception by the first repair registers,
wherein each memory system includes a second repair register and a decoder, wherein each of the respective decoders is operably coupled between the respective second repair register and the respective first repair register of the memory systems, and
wherein each memory system shifts compressed memory repair data for its memory module from the first repair register thereof through the decoder to the second repair register thereof for storage therein as decompressed memory repair data.
2. The integrated circuit of claim 1 , wherein the first memory system includes a state machine for shifting compressed memory repair data for its memory module from the first repair register through the decoder to the second repair register for storage therein.
3. The integrated circuit of claim 1 , wherein the store is a one-time programmable read-only memory (OTPROM).
4. The integrated circuit of claim 1 , wherein the memory module of the first memory system is a ternary content addressable memory (TCAM).
5. The integrated circuit of claim 4 , wherein the memory module of the second memory system is a cache.
6. The integrated circuit of claim 1 , wherein:
each memory system includes a built-in self-test (BIST) engine for generating memory repair data associated with its memory module, and
the first memory system includes an encoder operably coupled between the first repair register thereof and the second repair register thereof, and arranged to shift uncompressed repair data generated by the BIST engine from the second repair register thereof through the encoder to the first repair register thereof for storage therein as compressed memory repair data.
7. The integrated circuit of claim 6 , wherein the first memory system includes a state machine for shifting uncompressed repair data from the second repair register thereof through the encoder to the first repair register thereof for storage therein as compressed repair data.
8. The integrated circuit of claim 1 , wherein:
the processor disables at least one of the first and second memory systems depending on a pre-determined configuration of the integrated circuit; and
the integrated circuit includes:
at least one dummy register operably coupled to the processor for receiving memory repair data and connected in parallel across one of the first and second memory systems; and
a selector for receiving a control signal from the processor and selecting one of an output of a dummy register and an output of the connected memory system depending on the pre-determined configuration of the integrated circuit.